The development of brain-inspired spiking neural networks (SNNs) has great potential for neuromorphic edge computing applications, while challenges remain in optimizing power-efficiency and silicon utilization. Neurons, synapses and spike-based learning algorithms form the fundamental information processing mechanism of SNNs. In an effort to achieve compact and biologically plausible SNNs while restricting power consumption, we propose a set of new neuromorphic building circuits, including an analog Leaky Integrate-and-Fire (LIF) neuron circuit, configurable synapse circuits and Spike Driven Synaptic Plasticity (SDSP) learning algorithm circuits. Specifically, we explore methods to minimize large leakage current and device mismatch effects, and optimize the design of these neuromorphic circuits to enable low-power operation. A reconfigurable mixed-signal SNN is proposed based on the building circuits, allowing flexible configuration of synapse weights and attributes, resulting in enhanced SNN functionality and reduced unnecessary power consumption. This SNN chip is fabricated using 55 nm CMOS technology, and test results indicate that the proposed circuits have the ability to closely mimic the behaviors of LIF neurons, synapses and SDSP mechanisms. By configuring synaptic arrays, we established varied connections between neurons in the SNN and demonstrated that this SNN chip can implement Pavlov’s dog associative learning and binary classification tasks, while dissipating less energy per spike of the order of Pico Joules per spike at a firing rate ranging from 30 Hz to 1 kHz. The proposed circuits can be used as building blocks for constructing large-scale SNNs in neuromorphic processors.

Recent years have seen an increasing popularity in the development of brain-inspired neuromorphic hardware for neural computing systems. However, implementing very large scale simulations of neural networks in hardware is still an open challenge in terms of power efficiency, compactness, and biophysical resemblance. In an effort to design biologically plausible spiking neuron circuits while restricting power consumption, we propose a new subthreshold Leaky Integrate-and-Fire (LIF) neuron circuit designed using 22 nm FDSOI technology. In this circuit, problems of large leakage currents and device mismatch are effectively reduced by deploying the back-gate terminal of FDSOI technology for a tunable design. The proposed neuron is able to operate in two spiking frequency modes with tunable bias parameter setting of key transistors, and it results in complex firing behaviors, such as adaptation, chattering, and bursting, through varying bias voltages. We present circuit post-layout simulation results and demonstrate the biologically plausible neural dynamics. Compared with published state-of-the-art neuron circuits, the circuit dissipates ultra-low energy per spike, on the order of femtojoules per spike, at firing rates ranging from 30 Hz to 1 kHz. Furthermore, the circuit is proven to maintain a good robustness over process variation and Monte Carlo analysis, with relative error 3.02% at a firing rate of approximately 67.1 Hz.

A mixed-signal spiking neural network (SNN) chip is presented, and its radiation effect-Total Ionizing Dose (TID) was studied. The chip was fabricated in a 180 nm silicon-on-insulator (SOI) integration process with an area of 3.75 mm²; the total doses were set at 300 krad (Si), 500 krad (Si), and 1 Mrad (Si). The TID radiation experimental results showed that the average spike frequency and spike amplitude of the output signal of the SNN circuit decreased after the irradiation because of the leakage current caused by the charge trapped in the buried oxide. Sensitive nodes were identified through the analysis of the critical path of the circuit, and guidance toward a radiation-hardening neuron circuit was proposed. The proposed circuit maintains good robustness with firing frequency variation.