The complementary field-effect transistor (CFET) with stacked N-type FET (NFET) and P-type FET (PFET) is an attractive approach to shrink the footprint of multiple devices at circuit level and increase transistor density. Compared with traditional device structure, the unique geometry of CFET brings very different parasitics. In this work, we take the inverter as an exemplar CFET circuit building block and provide analytical compact models of calculating parasitic capacitance, which is critical to enable fast and accurate simulations at circuit level. The validity of the models is calibrated and verified with 3-D numerical simulations. A comparison between the CFET inverter with its same ground-rule gate-all-around FET (GAAFET) counterpart reveals the critical CFET design parameters and demonstrates performance advantage of CFET architecture.

The effect of the source/drain compressive stress on the mechanical stability of stacked Si nanosheets (NS) during the process of channel release has been investigated. The stress of the nanosheets in the stacking direction increased first and then decreased during the process of channel release by technology computer-aided design (TCAD) simulation. The finite element simulation showed that the stress caused serious deformation of the nanosheets, which was also confirmed by the experiment. This study proposed a novel channel release process that utilized multi-step etching to remove the sacrificial SiGe layers instead of conventional single-step etching. By gradually releasing the stress of the SiGe layer on the nanosheets, the stress difference in the stacking direction before and after the last step of etching was significantly reduced, thus achieving equally spaced stacked nanosheets. In addition, the plasma-free oxidation treatment was introduced in the multi-step etching process to realize an outstanding selectivity of 168:1 for Si_0.7Ge_0.3 versus Si. The proposed novel process could realize the channel release of nanosheets with a multi-width from 30 nm to 80 nm with little Si loss, unlocking the full potential of gate-all-around (GAA) technology for digital, analog, and radio-frequency (RF) circuit applications.

Impacts of source/drain (S/D) recess engineering on the device performance of both the gate-all-around (GAA) nanosheet (NS) field-effect transistor (FET) and FinFET have been comprehensively studied at 5 nm node technology. TCAD simulation results show that the device off-leakage, including subthreshold leakage through the channel (I_sub) and punch-through leakage (I_PT) in the sub-channel, is strongly related to the S/D recess process. Firstly, device electrical characteristics such as current density distributions, On/Off-state current (I_on, I_off), subthreshold swing (SS), RC delay, and gate capacitance (C_gg) are investigated quantitatively for DC/AC performance evaluation and comparison according to S/D lateral recess depth (L_rcs) variations. For both device types, larger L_rcs will result in a shorter effective channel length (L_eff), so that the I_on and I_off simultaneously increase. At the constant I_off, the L_rcs can be optimized to enhance the device’s drivability by ~3% and improve the device’s RC delay by ~1.5% due to a larger C_gg as a penalty. Secondly, S/D over recess depth (H_rcs) in the vertical direction severely affects the punch-through leakage in the Sub-Fin or bottom parasitic channel region. The NSFET exhibits less I_off sensitivity provided that it can be well controlled under 12 nm since the bottom parasitic channel is still gated. Furthermore, with both H_rcs and L_rcs accounted for in the device fabrication, the NSFET still shows better control of the off-leakage in the intrinsic and bottom parasitic channel regions and ~37% leakage reduction compared with FinFETs, which would be critical to enable further scaling and the low standby power application. Finally, the S/D recess engineering strategy has been given: a certain lateral recess could be optimized to obtain the best drive current and RC delay, while the vertical over-recess should be in tight management to keep the static power dissipation as low as possible.

A novel integration scheme of postgate single diffusion break (PG-SDB) has been proposed to enhance channel stress for Si gate-all-around (GAA) nanosheet field-effect transistors (NS-FET), based on TCAD simulations. Compared to conventional SDB and self-aligned SDB (SA-SDB), the proposed PG-SDB scheme implements SDB module after the replacement metal gate (RMG) process, so as to eliminate the stress relaxation to free surfaces. The channel stress has been boosted to +3.5 GPa/−4.7 GPa, for N/P NS-FETs, respectively. As a result, great drive capability as well as N/P current matching has been achieved in the PG-SDB GAA NS-FETs.

In this paper, nanosheet deformation during channel release has been investigated and discussed in Gate-All-Around (GAA) transistors. Structures with different source/drain size and stacked Si nanosheet lengths were designed and fabricated. The experiment of channel release showed that the stress caused serious deformation to suspended nanosheets. With the guidance of the experiment result, based on simulation studies using the COMSOL Multiphysics and Sentaurus tools, it is confirmed that the stress applied on the channel from source/drain plays an important role in nanosheet deformation during the fabrication process. The deformation of Si nanosheets would cause a serious degradation of the device performance due to an inability to control the work function of the metal gate. This study proposed that the uniformly stacked GAA nanosheets structure could be successfully demonstrated with suitable channel stress engineering provided by fitting S/D size and an appropriate channel length. The conclusions provide useful guidelines for future stacked GAA transistors’ design and fabrication.

Ferroelectric (FE) Hf _1-x Zr _x O ₂ (HZO) thin films have attracted considerable interest for their potential application in Ferroelectric Random-Access Memory (FeRAM) and Ferroelectric Field-Effect Transistors (FeFET), owing to their high dielectric constant, stability, and compatibility with CMOS processes. However, enhancing the polarization switching speed of HZO thin films remains a significant challenge. In this study, we successfully reduced the coercive field and improved the switching speed of HZO devices by integrating ferroelectric and antiferroelectric layers. We employed a high-speed pulsed measurement system with sub-nanosecond resolution to evaluate the switching speed of these devices. An ultrafast switching time of 780 ps at 2V was achieved, as supported by the nucleation-limited switching model. This work demonstrates a promising strategy for enhancing the switching speed in HZO films through structural engineering, offering valuable insights for practical device applications.