The effect of the source/drain compressive stress on the mechanical stability of stacked Si nanosheets (NS) during the process of channel release has been investigated. The stress of the nanosheets in the stacking direction increased first and then decreased during the process of channel release by technology computer-aided design (TCAD) simulation. The finite element simulation showed that the stress caused serious deformation of the nanosheets, which was also confirmed by the experiment. This study proposed a novel channel release process that utilized multi-step etching to remove the sacrificial SiGe layers instead of conventional single-step etching. By gradually releasing the stress of the SiGe layer on the nanosheets, the stress difference in the stacking direction before and after the last step of etching was significantly reduced, thus achieving equally spaced stacked nanosheets. In addition, the plasma-free oxidation treatment was introduced in the multi-step etching process to realize an outstanding selectivity of 168:1 for Si_0.7Ge_0.3 versus Si. The proposed novel process could realize the channel release of nanosheets with a multi-width from 30 nm to 80 nm with little Si loss, unlocking the full potential of gate-all-around (GAA) technology for digital, analog, and radio-frequency (RF) circuit applications.

In this paper, we demonstrate a comprehensive study of NF₃-based selective etching processes for inner spacer formation and for channel release, enabling stacked horizontal gate-all-around Si nanosheet transistor architectures. A cyclic etching process consisting of an oxidation treatment step and an etching step is proposed and used for SiGe selective etching. The cyclic etching process exhibits a slower etching rate and higher etching selectivity compared to the direct etching process. The cycle etching process consisting of Recipe 1, which has a SiGe etching rate of 0.98 nm/cycle, is used for the cavity etch. The process achieved good interlayer uniformity of cavity depth (cavity depth ≤ 5 ± 0.3 nm), while also obtaining a near-ideal rectangular SiGe etch front shape (inner spacer shape = 0.84) and little Si loss (0.44 nm@ each side). The cycle etching process consisting of Recipe 4 with extremely high etching selectivity is used for channel release. The process realizes the channel release of nanosheets with a multi-width from 30 nm to 80 nm with little Si loss. In addition, a selective isotropic etching process using NF₃/O₂/Ar gas mixture is used to etch back the SiN film. The impact of the O₂/NF₃ ratio on the etching selectivity of SiN to Si and the surface roughness of SiN after etching is investigated. With the introduction of O₂ into NF₃/Ar discharge, the selectivity increases sharply, but when the ratio of O₂/NF₃ is up to 1.0, the selectivity tends to a constant value and the surface roughness of SiN increases rapidly. The optimal parameter is O₂/NF₃ = 0.5, resulting in a selectivity of 5.4 and a roughness of 0.19 nm.

In this paper, a novel scheme for source/drain-first (S/D-first) full bottom dielectric isolation (BDI), i.e., Full BDI_Last, with integration of a sacrificial Si_0.5Ge_0.5 layer was proposed and demonstrated in a stacked Si nanosheet gate-all-around (NS-GAA) device structure using TCAD simulations. The proposed full BDI scheme flow is compatible with the main process flow of NS-GAA transistor fabrication and provides a large window for process fluctuations, such as the thickness of the S/D recess. It is an ingenious solution to insert the dielectric material under the source, drain and gate regions to remove the parasitic channel. Moreover, because the S/D-first scheme decreases the problem of high-quality S/D epitaxy, the innovative fabrication scheme introduces full BDI formation after S/D epitaxy to mitigate the difficulty of providing stress engineering in the full BDI formation before S/D epitaxy (Full BDI_First). The electrical performance of Full BDI_Last is demonstrated by a 4.78-fold increase in the drive current compared to Full BDI_First. Furthermore, compared to traditional punch through stoppers (PTSs), the proposed Full BDI_Last technology could potentially provide an improved short channel behavior and good immunity against parasitic gate capacitance in NS-GAA devices. For the assessed inverter ring oscillator (RO), applying the Full BDI_Last scheme allows the operating speed to be increased by 15.2% and 6.2% at the same power, or alternatively enables an 18.9% and 6.8% lower power consumption at the same speed compared with the PTS and Full BDI_First schemes, respectively. The observations confirm that the novel Full BDI_Last scheme incorporated into an NS-GAA device can be utilized to enable superior characteristics to benefit the performance of integrated circuits.

In advanced CMOS technology, a suitable spacer scheme is crucial to alleviate the effects of increasing parasitic resistance and capacitance on device performance as the critical dimensions shrinking. Low dielectric constant (low-k) films, possessing a tunable k value ranging from 3.5 to 6.5, were fabricated using plasma-enhanced atomic layer deposition in a single chamber. The fabrication process involved the deposition of the SiN film via SiH2I2 with N2 plasma, as well as the deposition of the SiOX, SiOCN, and SiON films using diisopropylamino silane with O2, Ar/O2, and N2/O2 plasmas, respectively. The introduction of groups containing carbon (C) tended to loosen the film structure, due to its weak bond strength with Si, thus made distinctions in structural and electrical stability. We developed such a process which can adjust the C-group concentration and O, N content to tune the film k value. The SiOx, SiOCN, SiON, and SiN films had high breakdown strength of 9.04, 7.23, 9.41, and over 11 MV cm−1, and meanwhile low leakage current density of 2.42 × 10−9, 4.78 × 10−8, 1.29 × 10−9, and 9.26 × 10−10 A cm−2, respectively. The films exhibited remarkable thermal stability, enhanced breakdown strength, and suppressed leakage with annealing treatment, which could be attributed to the desorption of —CHX groups. Moreover, the low-k materials demonstrated excellent step coverage both in the inner-spacer cavity and on sidewalls, exploring the potential application as spacers in advanced CMOS structure.

In this work, a novel vertical gate-all-around field-effect transistor (VGAAFET) structure is proposed for scaling CMOS technology. Compared to the traditional VGAAFET, the lengths of gate ( ${L} _{g}$ ), spacer ( ${L} _{\text {sp}}$ ), and source/drain ( ${L} _{{\text S}/{\text D}}$ ) are predefined by the Si/SiGe/Si/SiGe/Si epitaxial stacks. Benefiting from the decoupling of the ${L} _{g}$ , ${L} _{\text {sp}}$ , and ${L} _{{\text S}/{\text D}}$ from the contact gate pitch (CGP) in the VGAAFET, the ${L} _{g}$ and ${L} _{\text {sp}}$ have been optimized to enhance the device performance without extending the footprint. To address the structural asymmetry and reduce the parasitic resistance ( ${R} _{\text {para}}$ ) of the VGAAFET, the backside contacts (BSCs) technology is integrated. Compared to the frontside contacts (FSCs) VGAAFET, the bottom source/drain resistance ( ${R} _{\text {BotS}/\text {D}}$ ) is reduced by 46.5%, and the on-state normalized current ( ${I} _{\text {on},\text {norm}}$ ) is increased by 21.8% for BSC-VGAAFET. Additionally, by employing the extension region doping (ERD) technology to improve the electrical characteristics symmetry between n/p VGAAFETs, an enhanced n/p current ratio from 1.31 to 1.16 has been achieved. Furthermore, to benchmark the power, performance, and area (PPA) characteristics between the VGAAFET and lateral GAAFET (LGAAFET) at the circuit-level, the nand2 standard cells are designed at the same footprint, and evaluated in our design technology co-optimization (DTCO) platform. The results of the 15-stage ring oscillator (RO) demonstrate that at the same supply voltage ( ${V} _{\text {dd}}$ ) and footprint, the BSC-VGAAFET achieves 52.2% frequency improvement and 21.6% energy-delay product (EDP) reduction compared to the LGAAFET. Therefore, the BSC-VGAAFET is a promising transistor architecture for next-generation integrated circuits (ICs).