The effect of the source/drain compressive stress on the mechanical stability of stacked Si nanosheets (NS) during the process of channel release has been investigated. The stress of the nanosheets in the stacking direction increased first and then decreased during the process of channel release by technology computer-aided design (TCAD) simulation. The finite element simulation showed that the stress caused serious deformation of the nanosheets, which was also confirmed by the experiment. This study proposed a novel channel release process that utilized multi-step etching to remove the sacrificial SiGe layers instead of conventional single-step etching. By gradually releasing the stress of the SiGe layer on the nanosheets, the stress difference in the stacking direction before and after the last step of etching was significantly reduced, thus achieving equally spaced stacked nanosheets. In addition, the plasma-free oxidation treatment was introduced in the multi-step etching process to realize an outstanding selectivity of 168:1 for Si_0.7Ge_0.3 versus Si. The proposed novel process could realize the channel release of nanosheets with a multi-width from 30 nm to 80 nm with little Si loss, unlocking the full potential of gate-all-around (GAA) technology for digital, analog, and radio-frequency (RF) circuit applications.

Impacts of source/drain (S/D) recess engineering on the device performance of both the gate-all-around (GAA) nanosheet (NS) field-effect transistor (FET) and FinFET have been comprehensively studied at 5 nm node technology. TCAD simulation results show that the device off-leakage, including subthreshold leakage through the channel (I_sub) and punch-through leakage (I_PT) in the sub-channel, is strongly related to the S/D recess process. Firstly, device electrical characteristics such as current density distributions, On/Off-state current (I_on, I_off), subthreshold swing (SS), RC delay, and gate capacitance (C_gg) are investigated quantitatively for DC/AC performance evaluation and comparison according to S/D lateral recess depth (L_rcs) variations. For both device types, larger L_rcs will result in a shorter effective channel length (L_eff), so that the I_on and I_off simultaneously increase. At the constant I_off, the L_rcs can be optimized to enhance the device’s drivability by ~3% and improve the device’s RC delay by ~1.5% due to a larger C_gg as a penalty. Secondly, S/D over recess depth (H_rcs) in the vertical direction severely affects the punch-through leakage in the Sub-Fin or bottom parasitic channel region. The NSFET exhibits less I_off sensitivity provided that it can be well controlled under 12 nm since the bottom parasitic channel is still gated. Furthermore, with both H_rcs and L_rcs accounted for in the device fabrication, the NSFET still shows better control of the off-leakage in the intrinsic and bottom parasitic channel regions and ~37% leakage reduction compared with FinFETs, which would be critical to enable further scaling and the low standby power application. Finally, the S/D recess engineering strategy has been given: a certain lateral recess could be optimized to obtain the best drive current and RC delay, while the vertical over-recess should be in tight management to keep the static power dissipation as low as possible.

In this paper, nanosheet deformation during channel release has been investigated and discussed in Gate-All-Around (GAA) transistors. Structures with different source/drain size and stacked Si nanosheet lengths were designed and fabricated. The experiment of channel release showed that the stress caused serious deformation to suspended nanosheets. With the guidance of the experiment result, based on simulation studies using the COMSOL Multiphysics and Sentaurus tools, it is confirmed that the stress applied on the channel from source/drain plays an important role in nanosheet deformation during the fabrication process. The deformation of Si nanosheets would cause a serious degradation of the device performance due to an inability to control the work function of the metal gate. This study proposed that the uniformly stacked GAA nanosheets structure could be successfully demonstrated with suitable channel stress engineering provided by fitting S/D size and an appropriate channel length. The conclusions provide useful guidelines for future stacked GAA transistors’ design and fabrication.

In this paper, we demonstrate a comprehensive study of NF₃-based selective etching processes for inner spacer formation and for channel release, enabling stacked horizontal gate-all-around Si nanosheet transistor architectures. A cyclic etching process consisting of an oxidation treatment step and an etching step is proposed and used for SiGe selective etching. The cyclic etching process exhibits a slower etching rate and higher etching selectivity compared to the direct etching process. The cycle etching process consisting of Recipe 1, which has a SiGe etching rate of 0.98 nm/cycle, is used for the cavity etch. The process achieved good interlayer uniformity of cavity depth (cavity depth ≤ 5 ± 0.3 nm), while also obtaining a near-ideal rectangular SiGe etch front shape (inner spacer shape = 0.84) and little Si loss (0.44 nm@ each side). The cycle etching process consisting of Recipe 4 with extremely high etching selectivity is used for channel release. The process realizes the channel release of nanosheets with a multi-width from 30 nm to 80 nm with little Si loss. In addition, a selective isotropic etching process using NF₃/O₂/Ar gas mixture is used to etch back the SiN film. The impact of the O₂/NF₃ ratio on the etching selectivity of SiN to Si and the surface roughness of SiN after etching is investigated. With the introduction of O₂ into NF₃/Ar discharge, the selectivity increases sharply, but when the ratio of O₂/NF₃ is up to 1.0, the selectivity tends to a constant value and the surface roughness of SiN increases rapidly. The optimal parameter is O₂/NF₃ = 0.5, resulting in a selectivity of 5.4 and a roughness of 0.19 nm.

In this paper, a novel scheme for source/drain-first (S/D-first) full bottom dielectric isolation (BDI), i.e., Full BDI_Last, with integration of a sacrificial Si_0.5Ge_0.5 layer was proposed and demonstrated in a stacked Si nanosheet gate-all-around (NS-GAA) device structure using TCAD simulations. The proposed full BDI scheme flow is compatible with the main process flow of NS-GAA transistor fabrication and provides a large window for process fluctuations, such as the thickness of the S/D recess. It is an ingenious solution to insert the dielectric material under the source, drain and gate regions to remove the parasitic channel. Moreover, because the S/D-first scheme decreases the problem of high-quality S/D epitaxy, the innovative fabrication scheme introduces full BDI formation after S/D epitaxy to mitigate the difficulty of providing stress engineering in the full BDI formation before S/D epitaxy (Full BDI_First). The electrical performance of Full BDI_Last is demonstrated by a 4.78-fold increase in the drive current compared to Full BDI_First. Furthermore, compared to traditional punch through stoppers (PTSs), the proposed Full BDI_Last technology could potentially provide an improved short channel behavior and good immunity against parasitic gate capacitance in NS-GAA devices. For the assessed inverter ring oscillator (RO), applying the Full BDI_Last scheme allows the operating speed to be increased by 15.2% and 6.2% at the same power, or alternatively enables an 18.9% and 6.8% lower power consumption at the same speed compared with the PTS and Full BDI_First schemes, respectively. The observations confirm that the novel Full BDI_Last scheme incorporated into an NS-GAA device can be utilized to enable superior characteristics to benefit the performance of integrated circuits.

In this work, a novel self-aligned source/drain confinement (SA-SDC) scheme is proposed to enable the downsizing of gate-all-around (GAA) nanosheet (NS) field-effect transistors (FETs). Compared with the traditional diamond-shaped source/drain (S/D) epitaxy, the proposed SA-SDC scheme suppresses the lateral over expansion and facilitates wrap-around contact (WAC) formation, resulting in the decrease of device area, parasitic capacitance ( $\textit{C}_{\text{para}}$ ), and resistance ( $\textit{R}_{\text{para}}$ ). A calibrated 3-D TCAD simulation demonstrates a 35% reduction in the device RC delay for the SA-SDC NS FET. Considering various device structures and channel stress variations induced by diffusion break integration schemes, a comprehensive investigation of the 15-stage ring oscillator (RO) is conducted. By integrating the stress-enhanced postgate single diffusion break (PG-SDB) process, the SA-SDC NAND2 cell achieves an additional 21% reduction in the power dissipation or a 9% increase in the frequency. Power, performance, and area (PPA) are also collaboratively optimized for different applications using the quantitative quality factor. Particularly, the NAND2 cell is optimized within the constrained footprint. The cell, with 30–40-nm NS width of the n-type device, exhibits the optimal and robust performance for all the simulated technology/design options.