Shaahin Angizi

Dr. Shaahin Angizi

Department of Electrical and Computer Engineering, New Jersey Institute of Technology, Newark, NJ 07102, USA

Research Focus & Metrics

Academic Career Length

13Years (2014-Present)

(Calculated once Scilit publication data is synced: current year − year of first publication + 1)

Representative Publications

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1 June 2015 in Microelectronics Journal
Verified
Journal Article
Closed access
SSShadi Sheikhfaal
Shadi Sheikhfaal
Shaahin AngiziShaahin Angizi
Shaahin Angizi
SSSoheil Sarmadi
Soheil Sarmadi
MMMohammad Hossein Moaiyeri
Mohammad Hossein Moaiyeri
SSSamira Sayedsalehi
Samira Sayedsalehi

1 June 2014 in Journal of Low Power Electronics
Verified
Journal Article
Closed access
Shaahin AngiziShaahin Angizi
Shaahin Angizi
EAEsam Alkaldy
Esam Alkaldy
NBNader Bagherzadeh
Nader Bagherzadeh
KNKeivan Navi
Keivan Navi

1 January 2015 in Microelectronics Journal
Verified
Journal Article
Closed access
Shaahin AngiziShaahin Angizi
Shaahin Angizi
SSSoheil Sarmadi
Soheil Sarmadi
SSSamira Sayedsalehi
Samira Sayedsalehi
KNKeivan Navi
Keivan Navi

1 September 2016 in Journal of Computational Science
Verified
Journal Article
Closed access
FAFirdous Ahmad
Firdous Ahmad
GBGhulam Mohiuddin Bhat
Ghulam Mohiuddin Bhat
HKHossein Khademolhosseini
Hossein Khademolhosseini
SASaeid Azimi
Saeid Azimi
Shaahin AngiziShaahin Angizi
Shaahin Angizi
KNKeivan Navi
Keivan Navi

27 March 2019 in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Verified
Journal Article
Closed access
Shaahin AngiziShaahin Angizi
Shaahin Angizi
Zhezhi HeZhezhi He
Zhezhi He
AAAmro Awad
Amro Awad
DFDeliang Fan
Deliang Fan
In this paper, we propose MRIMA, as a novel magnetic RAM (MRAM)-based in-memory accelerator for nonvolatile, flexible, and efficient in-memory computing. MRIMA transforms current spin transfer torque magnetic random access memory (STT-MRAM) arrays to massively parallel computational units capable of working as both nonvolatile memory and in-memory logic. Instead of integrating complex logic units in cost-sensitive memory, MRIMA exploits hardware-friendly bit-line computing methods to implement complete Boolean logic functions between operands within a memory array in a single clock cycle, overcoming the multicycle logic issue in contemporary processing-in-memory (PIM) platforms. We present practical case studies to demonstrate MRIMA's acceleration for binary-weight and low bit-width convolutional neural networks (CNNs) as well as data encryption. Our device-to-architecture co-simulation results on CNN acceleration demonstrate that MRIMA can obtain 1.7× better energy-efficiency and 11.2× speed-up compared to ASICs, and 1.8× better energy-efficiency and 2.4× speed-up over the best DRAM-based PIM solutions. As an advanced encryption standard (AES) in-memory encryption engine, MRIMA shows ~77% and 21% lower energy consumption compared to CMOS-ASIC and recent domain-wall-based design, respectively.

1 March 2017 in Microprocessors and Microsystems
Verified
Journal Article
Closed access
ACAmir Mokhtar Chabi
Amir Mokhtar Chabi
ARArman Roohi
Arman Roohi
HKHossein Khademolhosseini
Hossein Khademolhosseini
SSShadi Sheikhfaal
Shadi Sheikhfaal
Shaahin AngiziShaahin Angizi
Shaahin Angizi
RDRonald F. DeMara
Ronald F. DeMara