Wanling Deng

Dr. Wanling Deng


Research Focus & Metrics

Academic Career Length

20Years (2007-Present)

(Calculated once Scilit publication data is synced: current year − year of first publication + 1)

Representative Publications

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13 December 2016 in IEEE Electron Device Letters
Verified
Journal Article
Closed access
JFJielin Fang
Jielin Fang
WDWanling Deng
Wanling Deng
XMXiaoyu Ma
Xiaoyu Ma
JHJunkai Huang
Junkai Huang
WWWeijing Wu
Weijing Wu
In this letter, for both non-degenerate conduction and degenerate conduction, a new compact model of amorphous oxide semiconductor thin-film transistors is developed. The contributions of the trapped and free charges are considered in the closed-form solutions of surface potential and drain current under a degenerate regime. Furthermore, proof of the model's accuracy has been obtained by comparisons with numerical results and measured data. The proposed scheme is capable of capturing real-device dc characteristics and of maintaining high computational efficiency, which provides a better platform to develop advanced surface-potential-based model for circuit simulation.

4 November 2011 in IEEE Transactions on Electron Devices
Verified
Journal Article
Closed access
WDWanling Deng
Wanling Deng
JHJunkai Huang
Junkai Huang
XLXiyue Li
Xiyue Li
An explicit approximation for surface potential as a function of terminal voltages is developed for partially depleted polysilicon thin-film transistors. The resulting model has taken both Gaussian deep states and exponential tail states into account, which provides a complete modeling for surface potential. Furthermore, a drain current model based on terms of surface potential is proposed. Surface potential and drain current calculations are successfully verified by comparisons with numerical and experimental ones.

13 February 2018 in IEEE Transactions on Electron Devices
Verified
Journal Article
Closed access
WDWanling Deng
Wanling Deng
JFJielin Fang
Jielin Fang
XWXixiong Wei
Xixiong Wei
WWWeijing Wu
Weijing Wu
JHJunkai Huang
Junkai Huang
A core scheme including dc and capacitance models of amorphous indium gallium zinc oxide thin-film transistors is presented based on terms of surface potential. Due to the intrinsic physical fact, carrier degeneracy is taken into account. A simpler symmetric quadrature version of charge-sheet model is adopted, which offers a new approach to deduce the expressions of current and terminal charges. Through the extensive comparisons between model results and numerical iterations or experimental data, the validity of the proposed models is strongly supported. The simplicity of algorithm and clear physical conception make the model suitable for circuit simulators.

3 December 2007 in Solid-State Electronics
Verified
Journal Article
Closed access
WDWanling Deng
Wanling Deng
XZXueren Zheng
Xueren Zheng
RCRongsheng Chen
Rongsheng Chen
YLYuan Liu
Yuan Liu

3 February 2016 in IEEE Transactions on Electron Devices
Verified
Journal Article
Closed access
FYFei Yu
Fei Yu
WDWanling Deng
Wanling Deng
JHJunkai Huang
Junkai Huang
XMXiaoyu Ma
Xiaoyu Ma
SCSonglin Chen
Songlin Chen
An explicit current-voltage model for cylindrical surrounding-gate polysilicon (poly-Si) transistors with a doped poly-Si channel is presented. It is based on an intermediate parameter which is derived analytically from the 1-D Poisson's equation and satisfies the corresponding boundary conditions. The surface and midpoint potentials are described as functions of this intermediate parameter. Furthermore, the drain currents in the different operational regions are analytically integrated. Our model results show good agreement with numerical and experimental data. The use of the explicit surface potential solution results in an easy implementation into circuit simulators.

26 September 2022 in IEEE Transactions on Electron Devices
Verified
Journal Article
Closed access
WYWeijie Ye
Weijie Ye
YLYuan Liu
Yuan Liu
BWBingqi Wang
Bingqi Wang
JHJunkai Huang
Junkai Huang
XXXiaoming Xiong
Xiaoming Xiong
WDWanling Deng
Wanling Deng
An improved model for the low-frequency noise (LFN) of amorphous indium–zinc-oxide thin-film transistors (a-IZO TFTs) is developed in this article. For a-IZO TFTs, the LFN is not only attributed to the oxide traps in the gate insulator but also affected by the discrete trap centers in the active-layer film. This makes the device has excess noise in the subthreshold region, which is obviously different from monocrystalline silicon (c-Si) MOSFETs. Therefore, we put forward an accurate and physically meaningful model to characterize this excess noise. For the subthreshold region, the charge of tail states in the channel is considered to describe the excess subthreshold noise, and the channel density of states (DOS) is extracted, confirming the effectiveness of the model. For the above-threshold region, the classic carrier number with correlated mobility fluctuation ( $\Delta N$ – $\Delta \mu $ ) mechanism has been investigated to explain the noise behavior. Furthermore, the proposed unified model is validated, and it has been successfully applied to a-IZO TFTs with different tail-state densities.