An explicit approximation for surface potential as a function of terminal voltages is developed for partially depleted polysilicon thin-film transistors. The resulting model has taken both Gaussian deep states and exponential tail states into account, which provides a complete modeling for surface potential. Furthermore, a drain current model based on terms of surface potential is proposed. Surface potential and drain current calculations are successfully verified by comparisons with numerical and experimental ones.

A core scheme including dc and capacitance models of amorphous indium gallium zinc oxide thin-film transistors is presented based on terms of surface potential. Due to the intrinsic physical fact, carrier degeneracy is taken into account. A simpler symmetric quadrature version of charge-sheet model is adopted, which offers a new approach to deduce the expressions of current and terminal charges. Through the extensive comparisons between model results and numerical iterations or experimental data, the validity of the proposed models is strongly supported. The simplicity of algorithm and clear physical conception make the model suitable for circuit simulators.

An explicit current-voltage model for cylindrical surrounding-gate polysilicon (poly-Si) transistors with a doped poly-Si channel is presented. It is based on an intermediate parameter which is derived analytically from the 1-D Poisson's equation and satisfies the corresponding boundary conditions. The surface and midpoint potentials are described as functions of this intermediate parameter. Furthermore, the drain currents in the different operational regions are analytically integrated. Our model results show good agreement with numerical and experimental data. The use of the explicit surface potential solution results in an easy implementation into circuit simulators.

An improved model for the low-frequency noise (LFN) of amorphous indium–zinc-oxide thin-film transistors (a-IZO TFTs) is developed in this article. For a-IZO TFTs, the LFN is not only attributed to the oxide traps in the gate insulator but also affected by the discrete trap centers in the active-layer film. This makes the device has excess noise in the subthreshold region, which is obviously different from monocrystalline silicon (c-Si) MOSFETs. Therefore, we put forward an accurate and physically meaningful model to characterize this excess noise. For the subthreshold region, the charge of tail states in the channel is considered to describe the excess subthreshold noise, and the channel density of states (DOS) is extracted, confirming the effectiveness of the model. For the above-threshold region, the classic carrier number with correlated mobility fluctuation ( $\Delta N$ – $\Delta \mu $ ) mechanism has been investigated to explain the noise behavior. Furthermore, the proposed unified model is validated, and it has been successfully applied to a-IZO TFTs with different tail-state densities.

A physical-based straightforward extraction technique for interface and bulk density of states in metal oxide semiconductor thin film transistors (TFTs) is proposed by using the capacitance–voltage (C–V) characteristics. The interface trap density distribution with energy has been extracted from the analysis of capacitance–voltage characteristics. Using the obtained interface state distribution, the bulk trap density has been determined. With this method, for the interface trap density, it is found that deep state density nearing the mid-gap is approximately constant and tail states density increases exponentially with energy; for the bulk trap density, it is a superposition of exponential deep states and exponential tail states. The validity of the extraction is verified by comparisons with the measured current–voltage (I–V) characteristics and the simulation results by the technology computer-aided design (TCAD) model. This extraction method uses non-numerical iteration which is simple, fast and accurate. Therefore, it is very useful for TFT device characterization.

The thermal analysis of GaN-based high electron-mobility transistors (HEMTs) is carried out from steady-state and transient aspects, respectively. An improved closed-form nonlinear thermal model based on device structure is proposed. In the steady-state case, the plane layer is added on the basis of the original partition, and the effect of thermal boundary resistance on channel temperature is also considered. In addition, the operating temperature of each gate finger is predicted based on the thermal coupling, and the nonlinear thermal model is extended to the transient by combining the thermal time constant. The validity of our presented model is verified by comparing the simulation results with the experimental data. Furthermore, this model is also embedded in the surface-potential-based current model to verify the self-heating effect in the circuits.