This letter presents a broadband multistage low-noise amplifier (LNA) in a 0.15- $\mu $ m GaAs pseudomorphic high-electron-mobility (pHEMT) process. The LNA employs multiple bandwidth extension techniques, including cascode, feedback, and gain-enhanced source–drain coupled line (SDCL). The SDCL enhances the gain by combining the source and drain signals and compensates the gain roll-off of the amplifier, which is first proposed in this letter to our knowledge. These techniques are adopted in a three-stage monolithic microwave integrated circuit (MMIC) LNA, achieving a wide bandwidth with high gain. The measured results show that the LNA obtains an average gain of 24.7 dB and a noise figure (NF) of 1.7–2.8 dB in 0.5–24 GHz, with a compact chip area of only 1.47 mm $^{2}$ .

This paper analyzes the main factors limiting the bandwidth expansion of low-noise amplifiers (LNA) and designs a broadband LNA with a bandwidth of 2-40.5 GHz. The LNA is designed using multiple bandwidth expansion methods, including cascode, resistance feedback, and cascode Darlington amplifier. The amplitude-frequency characteristics and bandwidth expansion principle of the three structures are studied theoretically based on the small-signal equivalent circuit model. Thanks to these techniques, a three-stage LNA is designed in a 0.15-μm GaAs pseudomorphic high-electron-mobility (pHEMT) process. The measured results show that the designed LNA achieves an average gain of 21.6 dB in 2-40.5 GHz while maintaining a noise figure (NF) below 3.6 dB. The measured output 1-dB gain compression point (OP1 dB) is from 4.5 to 12.8 dBm and the input/output return loss are better than 5 dB. The chip area is only 1.57 mm ² , including input and output test pads.

In this letter, a novel multiconductor coupled line (MCL) balun is presented for the implementation of a wideband double balanced mixer (DBM). The proposed balun utilizes an artificial transmission line (ATL) (composed of periodical shunt stubs), and manages to shorten the length by 65.1% compared with the three-line balun. Besides, in order to provide a point for intermediate frequency (IF) extraction, two sections of coupled lines are exclusively added behind local oscillator (LO) balun. And this structure also transmits LO signals to the diodes for mixing. Through the aforementioned operations, a compact balun and an 18–50 GHz mixer in 0.15- $\mu$ m GaAs pseudomorphic high electron mobility transistor (p-HEMT) process are designed. The measured results show that within the operation frequency, the phase and amplitude difference of the balun are lower than 3.5 $^{\circ}$ and 1.1 dB, respectively. The mixer dB conversion loss (CL) and 33 dB LO-to-RF isolation under 15 dBm LO power. The monolithic microwave integrated circuit (MMIC) area is 0.96 $\times$ 1.68 mm $^{2}$ , including all pads.

In this brief, a three-stage broadband cascode low noise amplifier (LNA) is proposed with transformer feedback and Darlington techniques. The first two stages use transformer feedback to provide low-frequency gain, and the Darlington structure is employed in the third stage to compensate for highfrequency gain. The additional transmission poles introduced by the transformer feedback increase the freedom of gain tuning with little effect on low-frequency gain, therefore facilitating the design of broadband LNAs. To verify the feasibility of bandwidth expansion of these two structures, the proposed LNA is designed and fabricated in a 0.15-μm GaAs pseudomorphic high electron mobility transistor (pHEMT) technology. The measured results show that the proposed LNA achieves an average gain of 23.4 dB and a minimum noise figure (NF) of 2.1 dB in the operating band from 0.5 GHz to 30 GHz. The power consumption of the LNA is 246 mW at 6 V/ -0.6 V DC bias. The LNA has a compact chip size with an area of 2.2 × 0.7 mm2, including test pads.

This paper presents a high-accuracy multifunction chip (MFC) with amplitude and phase control in X-band. The MFC is designed with a common leg structure and incorporates a 6-bit attenuator (ATT), a 6-bit phase shifter (PS), two gain compensation amplifiers (GCAs), three single pole double throw switches (SPDTs), and fourteen logic control circuits. However, cascading these blocks causes the change of the terminal impedances of the ATT and PS, which is detrimental to the accuracy. To solve this problem, the extra tunable interstage matching networks (IMNs) are introduced between each ATT and PS cell to alleviate the terminal impedance changes. The compensation capacitances are also applied to ATT to reduce the insertion phase shift. The receive and transmit modes switching is achieved by using four SPDTs. In addition, the resistance feedback is used in GCAs to compensate for passive losses and provide gain to the MFC. To validate the design scheme, the proposed MFC is fabricated in 0.15-μm GaAs pseudomorphic high-electron-mobility transistor (pHEMT) process. The measured results show that the MFC has excellent accuracy due to the introduction of IMNs. In the range of 8-11 GHz, the measured maximum root-mean-square (RMS) amplitude error of the MFC is less than 0.28 dB, and the maximum RMS phase error is less than 3.3°. Moreover, the MFC is achieved with a compact layout of 4.3 mm × 2.85 mm. Excellent performance and compact size make the MFC greatly potential in spaceborne phased array applications.