We have developed a scalable detector readout design for a 100 ps coincidence time resolution (CTR) time of flight (TOF) positron emission tomography (PET) detector technology. The basic scintillation detectors studied in this paper are based on 2 × 4 arrays of 3 × 3 × 10 mm 3 ‘fast-LGSO:Ce’ scintillation crystals side-coupled to 6 × 4 arrays of 3 × 3 mm 2 silicon photomultipliers (SiPMs). We employed a novel mixed-signal front-end electronic configuration and a low timing jitter Field Programming Gate Array-based time to digital converter for data acquisition. Using a 22 Na point source, >10 000 coincidence events were experimentally acquired for several SiPM bias voltages, leading edge time-pickoff thresholds, and timing channels. CTR of 102.03 ± 1.9 ps full-width-at-half-maximum (FWHM) was achieved using single 3 × 3 × 10 mm 3 ‘fast-LGSO’ crystal elements, wrapped in Teflon tape and side coupled to a linear array of 3 SiPMs. In addition, the measured average CTR was 113.4 ± 0.7 ps for the side-coupled 2 × 4 crystal array. The readout architecture presented in this work is designed to be scalable to large area module detectors with a goal to create the first TOF-PET system with 100 ps FWHM CTR.
24 May 2018 in IEEE Transactions on Very Large Scale Integration (VLSI) Systems
In this paper, a highly power-efficient class-AB-AB Miller op-amp is discussed. The structure uses gm enhancement based on local common-mode feedback to provide class-AB operation with enhanced effective gm, open-loop gain, unity-gain frequency, and slew rate (SR) without significant increase in quiescent power consumption. Utilization of a nonlinear load leads to large symmetric positive and negative SRs. Stability over an extremely wide range of capacitive loads is achieved through a combination of Miller and phase-lead compensations. The unity-gain frequency does not show sensitivity to capacitive load values. A test chip prototype fabricated in 0.18-μm CMOS technology shows 90.8-dB open-loop gain, 12.5-MHz bandwidth for a 25-pF load capacitance, and a factor 60 SR enhancement with maximum output current close to 1-mA and 43-μA total static current.
15 September 2021 in Biomedical Physics & Engineering Express
Positron Emission Tomography (PET) reconstructed image signal-to-noise ratio (SNR) can be improved by including the 511 keV photon pair coincidence time-of-flight (TOF) information. The degree of SNR improvement from this TOF capability depends on the coincidence time resolution (CTR) of the PET system, which is essentially the variation in photon arrival time differences over all coincident photon pairs detected for a point positron source placed at the system center. The CTR is determined by several factors including the intrinsic properties of the scintillation crystals and photodetectors, crystal-to-photodetector coupling configurations, reflective materials, and the electronic readout configuration scheme. The goal of the present work is to build a novel TOF-PET system with 100 picoseconds (ps) CTR, which provides an additional factor of 1.5–2.0 improvement in reconstructed image SNR compared to state-of-the-art TOF-PET systems which achieve 225–400 ps CTR. A critical parameter to understand is the optical reflector’s influence on scintillation light collection and transit time variations to the photodetector. To study the effects of the reflector covering the scintillation crystal element on CTR, we have tested the performance of four different reflector materials: Enhanced Specular Reflector (ESR) –coupled with air or optical grease to the scintillator; Teflon tape; BaSO 4 paint alone or mixed with epoxy; and TiO 2 paint. For the experimental set-up, we made use of 3 × 3 × 10 mm 3 fast-LGSO:Ce scintillation crystal elements coupled to an array of silicon photomultipliers (SiPMs) using a novel ‘side-readout’ configuration that has proven to have lower variations in scintillation light collection efficiency and transit time to the photodetector. Results : show CTR values of 102.0 ± 0.8, 100.2 ± 1.2, 97.3 ± 1.8 and 95.0 ± 1.0 ps full-width-half-maximum (FWHM) with non-calibrated energy resolutions of 10.2 ± 1.8, 9.9 ± 1.2, 7.9 ± 1.2, and 8.6 ± 1.7% FWHM for the Teflon, ESR (without grease), BaSO 4 (without epoxy) and TiO 2 paint treatments, respectively.
31 May 2017 in International Journal of Circuit Theory and Applications
We have evaluated the coincidence time resolution (CTR) performance of four different mixed-signal front-end electronic readout configurations with the goal to achieve 100 picoseconds (ps) CTR. The proposed TOF-PET detector elements are based on two $3{\times } 3{\times }10$ mm 3 “fast LGSO” crystal segments, side coupled to linear arrays of $3{\times }3$ mm 2 silicon photomultipliers (SiPMs), to form a total crystal length of 20 mm. We studied multiple configurations and components for the front-end readout: 1) high speed radio frequency (RF) amplifiers; 2) an ASIC-based discriminator; 3) a combination of RF amplifier, balun transformer, and discriminator ASIC; and 4) combination of balun transformer and discriminator ASIC. Using two $3{\times } 3{\times }10$ mm 3 fast LGSO crystals side coupled to a linear array of three SiPMs, coincidence data were experimentally acquired for each readout configuration in combination with a low jitter field-programmable gate array (FPGA)-based time-to-digital converter (TDC). After evaluating the timing performance of the three readout schemes, the best CTR value of 99.4 ± 1.9 ps FWHM was achieved for configuration (3), which is more than 20 ps better than the results achieved using configurations (1), (2), and (4).
19 April 2017 in IEEE Transactions on Circuits and Systems II: Express Briefs
This paper proposes a fully differential track and hold circuit using a new DC offset compensation scheme. It stores an amplified version of the offset during the hold phase, which is used in attenuated fashion during the track phase to compensate offset. This scheme is less sensitive to charge injection and other errors than conventional offset compensation schemes. Experimental results of a test chip in 0.18 μm CMOS technology verify the proposed scheme.