In recent times, much-coveted memristor emulators have found their use in a variety of applications such as neuromorphic computing, analog computations, signal processing, etc. Thus, a 100 MHz flux-controlled memristor emulator is proposed in this research brief. The proposed memristor emulator is designed using a single differential voltage current conveyor (DVCC), three PMOS transistors, and one capacitor. Among three PMOS transistors, two transistors are used to implement an active resistor, and one transistor is used as the multiplier required for the necessary memristive behaviors. Through simple adjustment of the switch, the proposed emulator can be operated in incremental as well as decremental configurations. The simulations are performed using a 180 nm technology node to validate the proposed design and are experimentally verified using AD844AN and CD4007 ICs. The memristor states of the proposed emulator are perfectly retained even in the absence of external stimuli, thereby ascertaining the non-volatility behavior. The robustness of the design is further analyzed using the PVT and Monte Carlo simulations, which suggest that the circuit operation is not hindered by the mismatch and process variations. A simple neuromorphic adaptive learning circuit based on the proposed memristor is also designed as an application.

In this article, we have proposed an electronic tunable grounded meminductor emulator (MIE) using a single voltage difference transconductance amplifier (VDTA). Along with one VDTA, two MOSFETs and two capacitors are used in the proposed MIE. Overall, the proposed MIE requires only 18 MOS transistors and two grounded capacitors. The performance of the proposed MIE was validated using Cadence Virtuoso with a 180-nm CMOS library. The layout area of the emulator is only 1081 $\mu$ m $^{2}$ . The proposed design operates up to 25 MHz. To validate the theoretical and simulation results, an experiment was performed using CA3080 ICs and experimental results validate the simulated result. The power consumption of the proposed design is 5.93 mW.

This article describes a low-voltage, low-power fractional-order low-pass filter (FO-LPF) of order 1 + α, which is implemented using a voltage differencing differential difference amplifier (VDDDA). The VDDDA structure is implemented using the bulk-driven metal oxide semiconductor transistor technique. The transistors operate in the subthreshold region to maintain low-supply voltage and low-power consumption. The FO-LPF structure implemented using this VDDDA structure is compact. It includes three VDDDAs and three grounded capacitors along with two active resistors implemented using MOS transistors. In addition, this filter structure provides electronic tuning of its order and cut-off frequency through the bias current of the active component used. The effects of tracking error and parasitics on the functionality of the proposed FO-LPF were investigated. The VDDDA and filter operate at ±300 mV and dissipate only 207 nW and 663 nW of power, respectively. Thus, the VDDDA structure and filter are suitable for low-voltage and low-power operation. Layouts of the proposed VDDDA as well as the FO-LPF were designed in the Cadence Virtuoso environment. Post-layout simulation results of the designed circuits imply that they are suitable for fabrication. Noise, total harmonic distortion, Monte-Carlo, and PVT analyses were also performed.