This paper proposes a charged controlled emulator model for memristor and memcapacitor using second-generation Current Conveyor (CCIIs) and Analog Multiplier (AM). The grounded and floating mem-element circuits have been designed using two CCIIs and one multiplier in addition to some passive components. The grounded type of design requires three resistors and three capacitors while floating design necessitates only two resistors and two capacitors. With the help of a switch, the proposed design can be easily switched into a memristor or memcapacitor. The proposed emulator model has been theoretically analyzed and simulated in PSpice to substantiate the effectiveness and accuracy. The practicability of the circuit has been established using commercially available ICs AD844AN and AD633JN. Non-linear characteristics of the proposed memristor emulator have been used to design a chaotic system.

In recent times, much-coveted memristor emulators have found their use in a variety of applications such as neuromorphic computing, analog computations, signal processing, etc. Thus, a 100 MHz flux-controlled memristor emulator is proposed in this research brief. The proposed memristor emulator is designed using a single differential voltage current conveyor (DVCC), three PMOS transistors, and one capacitor. Among three PMOS transistors, two transistors are used to implement an active resistor, and one transistor is used as the multiplier required for the necessary memristive behaviors. Through simple adjustment of the switch, the proposed emulator can be operated in incremental as well as decremental configurations. The simulations are performed using a 180 nm technology node to validate the proposed design and are experimentally verified using AD844AN and CD4007 ICs. The memristor states of the proposed emulator are perfectly retained even in the absence of external stimuli, thereby ascertaining the non-volatility behavior. The robustness of the design is further analyzed using the PVT and Monte Carlo simulations, which suggest that the circuit operation is not hindered by the mismatch and process variations. A simple neuromorphic adaptive learning circuit based on the proposed memristor is also designed as an application.

In this article, we have proposed an electronic tunable grounded meminductor emulator (MIE) using a single voltage difference transconductance amplifier (VDTA). Along with one VDTA, two MOSFETs and two capacitors are used in the proposed MIE. Overall, the proposed MIE requires only 18 MOS transistors and two grounded capacitors. The performance of the proposed MIE was validated using Cadence Virtuoso with a 180-nm CMOS library. The layout area of the emulator is only 1081 $\mu$ m $^{2}$ . The proposed design operates up to 25 MHz. To validate the theoretical and simulation results, an experiment was performed using CA3080 ICs and experimental results validate the simulated result. The power consumption of the proposed design is 5.93 mW.

A compact MOSFET-C floating/grounded meminductor emulator (MIE) model is presented for high operating frequency and low power operation. The proposed MIE uses only 22 MOSFETs and two capacitors. Its performance is theoretically analyzed and rigorously verified using the Cadence Virtuoso software and hardware prototypes. The proposed MIE operates appropriately for a wide range of frequencies up to 5 MHz with $590 \mu \text{W}$ power consumption at a 180nm CMOS technology node and manifests important signature properties. The MIE layout area in 180 nm CMOS technology is $13107.5 \mu \text{m}^{2}$ . To analyze the effects of statistical variations in MIE elements, extensive Monte Carlo simulations have been performed to demonstrate the robustness of the proposed MIE. For experimental validation, hardware prototypes have been developed and tested successfully. An MIE-based adaptive learning neuromorphic circuit is presented to show that it can mimic the behavioral responses of amoeba under varying environments such as temperature.