The Z²-FET operation as capacitorless DRAM is analyzed using advanced 2-D TCAD simulations for IoT applications. The simulated architecture is built based on actual 28-nm fully depleted silicon-on-insulator devices. It is found that the triggering mechanism is dominated by the front-gate bias and the carrier's diffusion length. As in other FB-DRAMs, the memory window is defined by the ON voltage shift with the stored body charge. However, the Z²-FET's memory state is not exclusively defined by the inner charge but also by the reading conditions.

2-D numerical simulations are used to demonstrate the Z²-FET as a competitive embedded capacitor-less dynamic random access memory cell for low-power applications. Experimental results in 28-nm fully depleted-silicon on insulator technology are used to validate the simulations prior to downscaling tests. Default scaling, without any structure optimization, and enhanced scaling scenarios are considered before comparing the bit cell area consumption and integration density with other eDRAM cells in the literature.

In this work, a functional Z2-FET DRAM memory matrix is experimentally demonstrated for the first time. Word-level operation with simultaneous reading and programming accesses is successfully proved. Disturbance is also explored, and the results demonstrate bitline disturbance immunity. Furthermore, the fabricated memory matrix, which includes only one selector per word-line, facilitates the scalability of the memory for increasing array dimensions.

Thermal effects are a major concern for efficient cryoCMOS circuit design. This work presents an experimental analysis of self-heating (SH) effects and thermal propagation in fully depleted silicon-on-insulator (FD-SOI) technology, measured from room temperature (300 K) down to 4.2 K, using the gate resistance thermometry technique. The channel temperature increase and the in-plane temperature profile were investigated and analytically modeled, together with the thermal coupling between simultaneously operating devices. We demonstrated a major constraint for extremely low-temperature operation due to abrupt channel temperature rise even at sub-1 mW input power, which propagates over hundreds of nanometers along the Si layer. Thermal coupling was identified as a source for SH aggravation, and needs to be particularly optimized to limit the heating of cryo-circuits.

Seeking to circumvent conventional computing bottlenecks, hardware alternatives, from brain-inspired designs to cryogenic quantum systems, necessitate integrating emerging non-volatile memories. Yet, the immaturity and unreliability of cryogenic-compatible memories hinder scalable computing advancements. This study characterizes 28 nm FD-SOI substrate-embedded Ge-rich Ge₂Sb₂Te₅ phase change memories (ePCMs) down to 12 K to overcome these hurdles. It reveals that ePCMs is cryogenic compatible and can encode multiple resistance states with minimal drift, essential for advanced computing solutions. Through simulations, the ePCM’s impact on a spiking neural network (SNN) performing MNIST classification is evaluated. The SNN maintains high accuracy for extended periods of 2 years at cryogenic temperatures, while an accuracy drop of 10.8% is observed at room temperature. These results highlight the potential of multilevel ePCMs in brain-inspired cryogenic computing applications, offering a promising avenue for the evolution of unconventional computing systems.