Caravel is an open-source project developed by Efabless for creating custom System-on-Chips (SoCs). It includes the design of a configurable chip, development tools, and documentation. The Caravel SoC includes a RISC-V with the Instruction Set Architecture RV32I. One of the key features of Caravel is its open-source nature. In this article, the Vector Accelerator Unit for the Caravel SoC template is presented to increase the RISC-V capabilities, allowing parallel data processing through 14 vector operations. The accelerator is based on 4 Arithmetic Logic Units connected directly to the RISC-V through Logic Analyzer port and the General-Purpose Input/Output (GPIO) port. The total area of this accelerator is less than 20% of the User Project Wrapper area allowing the user to implement their custom designs in 8.4256 mm.

The typical Integrated Circuit (IC) development process commences with formulating specifications in natural language and subsequently proceeds to Register Transfer Level (RTL) implementation. RTL code is traditionally generated through manual efforts, using Hardware Description Languages (HDL) such as VHDL or Verilog. High-Level Synthesis (HLS), on the other hand, converts programming languages to HDL; these methods aim to streamline the engineering process, minimizing human effort and errors. Currently, Electronic Design Automation (EDA) algorithms have been improved with the use of AI, with new advancements in commercial (such as ChatGPT, Bard, among others) Large Language Models (LLM) and open-source tools presenting an opportunity to automate the chip design process. This paper centers on the creation of AI by AI, a Convolutional Neural Network (CNN) IC entirely developed by an LLM (ChatGPT-4), and its manufacturing with the first fabricable open-source Process Design Kit (PDK), SKY130A. The challenges, opportunities, advantages, disadvantages, conversation flow, and workflow involved in CNN IC development are presented in this work, culminating in the manufacturing process of AI by AI using a 130 nm technology, marking a groundbreaking achievement as possibly the world’s first CNN entirely written by AI for its IC manufacturing with a free PDK, being a benchmark for systems that can be generated today with LLMs.

This article addresses a novel methodology for the utilization of Field Programmable Gate Array (FPGA) accelerators in on-board Synthetic Aperture Radar (SAR) processing routines. The methodology consists of using High-Level Synthesis (HLS) to create Intellectual property (IP) blocks and using the Reusable Integration Framework for FPGA Accelerators (RIFFA) to develop a Peripheral Component Interconnect express (PCIe) interface between the Central Processing Unit (CPU) and the FPGA, attaining transfer rates up to 15.7 GB/s. HLS and RIFFA reduce development time (between fivefold and tenfold) by using high-level programming languages (e.g., C/C++); moreover, HLS provides optimizations like pipeline, cyclic partition, and unroll. The proposed schematic also has the advantage of being highly flexible and scalable since the IPs can be exchanged to perform different processing routines, and since RIFFA allows employing up to five FPGAs, multiple IPs can be implemented in each FPGA. Since Fast Fourier Transform (FFT) is one of the main functions in SAR processing, we present a FPGA accelerator in charge of the reordering stage of VEC-FFT (an optimized version of FFT) as a proof of concept. Results are retrieved in reversed bit order, and the conventional reordering function may consume more than half of the total clock cycles. Next, to demonstrate flexibility, an IP for matrix transposition is implemented, another computationally expensive process in SAR due to memory access.

The main objective of this work is to provide a comprehensive explanation of the Register Transfer Level (RTL) to Graphic Data System II (GDSII) flow for designing custom Field-Programmable Gate Array (FPGA) architectures at the 130 nm technology node using the SKY130 Process Design Kit (PDK). By leveraging open-source tools—specifically OpenLane and OpenFPGA—this study details the methodology and implementation steps required to generate a GDSII layout of a custom FPGA. OpenLane offers an integrated RTL-to-GDSII flow by combining multiple Electronic Design Automation (EDA) tools, while OpenFPGA enables the construction of flexible and customizable FPGA architectures. The article covers key aspects of the RTL-to-GDSII workflow, including RTL file configuration, the utilization of configuration variables for physical design, hierarchical chip design, macro and core implementation, chip-level integration, and gate-level simulation. Experimental results validate the proposed workflow, showcasing the successful transformation from RTL to GDSII. The findings of this research provide valuable insights for researchers and engineers in the FPGA design field, advancing the state of the art in FPGA architecture development.

The SKY130 Process Design Kit (PDK) offers limited options for Static Random-Access Memory (SRAM) configurations, providing only three predefined memory sizes: $8\times 1024$ , $32\times 256$ , and $32\times 512$ , this poses a challenge for designers who require memories with different characteristics, as they must either design an entire memory architecture from scratch or resort to interleaving techniques with the available memory configurations. To address this issue, we present a novel framework that automates the generation of multiple memory arrays with custom floorplans, leveraging the concept of interleaving memory. Our framework enables designers to create various sizes and configurations memories by combining and interleaving the existing SKY130 PDK memories, additionally, the framework allows designers to easily specify their desired memory size, word length, floorplan, and other essential parameters. The framework then automatically generates multiple memory arrays that meet the specified requirements. Furthermore, it provides the files required by OpenLane, facilitating the seamless integration of these memories into the Register Transfer Level (RTL) to Graphic Data System II (GDSII) flow. The key advantage of our framework lies in its ability to streamline the creation of custom memories by automating the interleaving process and offering flexibility in floorplan design. This significantly reduces design time and effort, empowering designers to efficiently create memories with specific characteristics while adhering to the limitations of the SKY130 PDK. The framework thus serves as a valuable tool for memory design in the context of the SKY130 PDK, opening doors for more efficient and optimized chip designs.

This article explores the evolution of integrated circuits $\left(ICs\right)$, highlighting the fundamental role of open source Electronic Design Automation (EDA) tools in their development. It describes the IC’s design flow, differentiating between Front-end and Back-end design stages, and details the process of implementing the digital stage in offset quadrature phase-shift keying (OQPSK) modulation in an IC, including its hardware description language (HDL), the implementation test in the field-programmable gate array (FPGA), and the physical layout using the first manufactured open source process design kits (PDKs) in Global Foundries’ 180 nm, as well as the use of OpenLane and Caravel. To conclude, the results of the physical tests obtained from the digital modulation are presented, as well as the performance of the raised cosine shaping filter.