Caravel is an open-source project developed by Efabless for creating custom System-on-Chips (SoCs). It includes the design of a configurable chip, development tools, and documentation. The Caravel SoC includes a RISC-V with the Instruction Set Architecture RV32I. One of the key features of Caravel is its open-source nature. In this article, the Vector Accelerator Unit for the Caravel SoC template is presented to increase the RISC-V capabilities, allowing parallel data processing through 14 vector operations. The accelerator is based on 4 Arithmetic Logic Units connected directly to the RISC-V through Logic Analyzer port and the General-Purpose Input/Output (GPIO) port. The total area of this accelerator is less than 20% of the User Project Wrapper area allowing the user to implement their custom designs in 8.4256 mm.

The main objective of this work is to provide a comprehensive explanation of the Register Transfer Level (RTL) to Graphic Data System II (GDSII) flow for designing custom Field-Programmable Gate Array (FPGA) architectures at the 130 nm technology node using the SKY130 Process Design Kit (PDK). By leveraging open-source tools—specifically OpenLane and OpenFPGA—this study details the methodology and implementation steps required to generate a GDSII layout of a custom FPGA. OpenLane offers an integrated RTL-to-GDSII flow by combining multiple Electronic Design Automation (EDA) tools, while OpenFPGA enables the construction of flexible and customizable FPGA architectures. The article covers key aspects of the RTL-to-GDSII workflow, including RTL file configuration, the utilization of configuration variables for physical design, hierarchical chip design, macro and core implementation, chip-level integration, and gate-level simulation. Experimental results validate the proposed workflow, showcasing the successful transformation from RTL to GDSII. The findings of this research provide valuable insights for researchers and engineers in the FPGA design field, advancing the state of the art in FPGA architecture development.

This paper presents the design of a new neuro-generator of pseudorandom number type PRNG Pseudorandom Number Generator, which produces complex sequences with an adequate bit distribution. The circuit is connected to a neuronal module with six impulse neurons with different behaviors: spike frequency adaptation, phasic spiking, mixed mode, phasic bursting, tonic bursting and tonic spiking. This module aims to generate a non-periodic signal that becomes the clock signal for one of the LFSRs Linear Feedback Shift Register that the neuro-generator has. To verify its correct operation, the neuro-generator was subjected to a series of tests where the frequencies of the impulse neurons were modified. This modification allows the generation of a greater number of pulses at the output of the neuronal module, to obtain sequences with different characteristics that pass different NIST statistical tests (National Institute of Standards and Technology of U.S.). The results show that the new neuro-generator maintains pseudo-randomness in the sequences obtained with different frequencies and it can be implemented on a reconfigurable FPGA Field Programmable Gate Array Virtex 7 xc7vx485t-2ffg1761 device. Therefore, it can be used for applications such as biological systems.

Two fixed-point (FP) square root designs based on a bit-by-bit non-restoring algorithm are unfolded, and compared to a FP pipelined design based on the same algorithm. One of them is unfolded from a bit-serial design, while the other design is unfolded from a smaller version of the pipelined design that has a digit size of 2, for this reason, it is cataloged as “unfolding based”. Hardware utilization is estimated with the theoretical use in the RTL designs and the synthesis report as an auxiliary tool. Results show that the “unfolding based” design is comparable and even surpasses the pipelined design when it comes to outputting a first result, being 19.47% faster and using 32.59% of memory of the pipelined design.

The image processing nowadays is a field in development, many image filtering algorithms are tested every day; however, the main hurdles to overcome are the difficulty of implementation or the time response in a general purpose processors. When the amount of data is too big, a specific hardware accelerator is required because a software implementation or a generic processor is not fast enough to respond in real time. In this paper optimal hardware implementation is proposed for extracting edges and noise reduction of an image in real time. Furthermore, the hardware configuration is flexible with the ability to select between power and area optimization or speed and performance. The results of algorithms implementation are reported.

En este trabajo se describe la relevancia de la conversión de señales eléctricas discretas a señales en el dominio del tiempo, en otras palabras, la conversión digital analógica. Para ello existe el convertidor digital a analógico (CDA), el cual permite la utilización de señales en modo de corriente o voltaje variantes en el tiempo, las cuales se utilizan para interactuar con el mundo real, ya que por lo general las señales analógicas son utilizadas por los actuadores, las bocinas, las antenas, etc. Los CDA constan de varios subcircuitos como las fuentes y espejos de corriente, los pares diferenciales, los arreglos R-2R y, se explican y diseñan para conformar un CDA completo, la simulación y el diseño asistido por computadora de un CDA utilizando transitores de la tecnología CMOS, fueron cruciales para este diseño.