This paper deals with the definition and analysis of a complete electronic system for the detection and monitoring of stability characteristics in complex scenarios such as structural elements or environmental events. For instance, it may be successfully adopted to detect rockfall events on protection barriers, as well as to monitor landslides or the integrity of structures like bridges and buildings. The system is completely autonomous thanks to the implementation of an energy harvesting architecture and realizes a wireless sensor network whose nodes are auto-configurable, making it possible to freely arrange them in situ. The continuously collected data are relative to acceleration, inclination, position, and temperature of each node. These data are transmitted and stored on a remote web server devoted to the automatic management of alarms and accessible for data consulting. The proposed system is currently operating in different experimental fields in Italy.

This paper describes a method for the stability analysis and stabilization criteria in multi-device paralleled power amplifiers (PA) under large-signal operating conditions. The symmetry of the amplifier is exploited for a simple and effective study of odd- and even-order modes. The overall stability analysis is transformed into a sequence of analyses on single-mode single-transistor large-signal equivalent amplifiers, which are carried out by using a conversion matrix approach. Examples of application of the method are provided on a 9-GHz GaAs pHEMT monolithic-microwave integrated-circuit (MMIC) PA and a 590-MHz power silicon bipolar hybrid microwave integrated-circuit (HMIC) PA.

In this study, a two-stage simulation method is presented for the efficient design of frequency dividers using harmonic balance. The first stage uses a modified conversion matrix approach to select the subharmonic loads of the active element enabling the frequency division by a given order N. The second stage makes use of an auxiliary generator to obtain and modify the sub-harmonic-power curve versus the input power or input frequency. Systematic simulation tools are used to eliminate common hysteresis phenomena, which require additional constraints to minimize the disturbance of the original frequency-division bands and output power. A harmonic-balance technique to distinguish between subcritical flip bifurcations, associated with hystereses, and supercritical ones is presented, to our knowledge, for the first time. A technique is also derived to transform subcritical bifurcations into supercritical ones. The techniques have been successfully applied to a frequency divider by 2 at 630 MHz.

A low‐noise tunable filter with high dynamic range and minimum power consumption is presented and addressed with circuit details. It is based on an active solution simulating an inductive behaviour that allows improving the filter quality factor without affecting the noise performance. The low‐order bandpass filter is realised with minimum number of components and it is suitable to be integrated in integrated circuit or used in hybrid transceiver and modern reconfigurable radio systems. A prototype board with discrete components has been fabricated and tested with good results.

In this paper two new first order filter topologies realizing low-pass/all-pass (LP/AP) and low-pass/high-pass (LP/HP) outputs using electronically controllable second generation voltage conveyors (CVCIIs) are presented. Unlike second generation voltage conveyors (VCII), in CVCII each performance parameter, including ports, parasitic impedances, current and/or voltage gains can be electronically varied. Here, in particular, the proposed filter topologies are based on two CVCIIs, one resistor and one capacitor. In the first topology ${\mathrm{V}}_{\mathrm{LP}}$/${\mathrm{I}}_{\mathrm{AP}}$/${\mathrm{V}}_{\mathrm{AP}}$ and in the second topology ${\mathrm{I}}_{\mathrm{LP}}$/${\mathrm{V}}_{\mathrm{LP}}$/${\mathrm{I}}_{\mathrm{HP}}$/${\mathrm{V}}_{\mathrm{HP}}$ outputs are achievable, respectively. However, the current and voltage outputs are not achievable simultaneously and a floating capacitor is used. A control current (${\mathrm{I}}_{\mathrm{con}}$) is used to change the first CVCII Y port impedance, which sets the filter −3 dB frequency (${\mathrm{f}}_0$) of all the outputs. Moreover, in the second topology, the gains of HP and AP outputs are electronically adjusted by means of a control voltage (${\mathrm{V}}_{\mathrm{con}}$). Favorably, no restricting matching condition is necessary. PSpice simulations using 0.18 µm CMOS technology and supply voltages of ±0.9V show that by changing ${\mathrm{I}}_{\mathrm{con}}$ from 0.5 µA to 50 µA, ${\mathrm{f}}_0$ is varied from 89 kHz to 1 MHz. Similarly, for a ${\mathrm{V}}_{\mathrm{con}}$ variation from −0.9 V to 0.185 V, the gains of ${\mathrm{I}}_{\mathrm{AP}}$ and ${\mathrm{I}}_{\mathrm{HP}}$ vary from 30 dB to 0 dB and those of ${\mathrm{V}}_{\mathrm{AP}}$ and ${\mathrm{V}}_{\mathrm{HP}}$ vary from 100 dB to 20 dB. The total harmonic distortion (THD) is about 8%. The power consumption is from 0.385 mW to 1.057 mW.