This paper introduces a continuous-time low-pass sigma-delta modulator operating with a seven-phase 400 MHz clocking scheme to control time-based processing in the 3-bit two-step quantizer and main digital-to-analog converter (DAC). An on-chip voltage-controlled oscillator and a complementary injection-locked frequency divider are utilized for low-jitter clock signal generation with multiple phases, allowing 3-bit pulse-width modulated feedback with a single-element DAC to avoid performance degradation from unit element mismatch problems associated with conventional multi-bit DACs. Fabricated in a standard 0.18 μm CMOS technology, the 5th-order modulator achieves a peak SNDR of 67.7 dB in 25 MHz bandwidth, consumes 48 mW from a 1.8 V supply, and occupies a die area of 2.6 mm ² . The modulator has a measured SFDR of 78 dB and in-band IM3 under -72 dB with -2 dBFS two-tone signal power.

Two high-linearity inductorless broadband low-noise transconductance amplifiers (LNTAs) employing noise and distortion cancellation techniques are presented. The core design employs a common-gate input stage and a common-source error-amplifier (EA) stage. Stacked PMOS-NMOS topology enables large-signal operation while the drain current is reused. The high linearity performance is achieved by the derivative superposition of the pMOS and nMOS transistors that reduce the third-order distortion due to second-order interaction between input stage and EA stage. Critical design issues are carefully investigated along with the performance tradeoffs. In the fully differential architecture, the first LNTA covers 0.1-2-GHz bandwidth and achieves a minimum noise figure (NF) of 3 dB, third-order input intercept point (IIP3) of 10 dBm, and a 1-dB compression point of 0 dBm while dissipating 30.2 mW of dc power. The second lower power LNTA with bulk-driven technique achieves a minimum NF of 3.4 dB, IIP3 of 11 dBm, 0.1-3-GHz bandwidth at 16 mW of power consumption. Each LNTA occupies an active area of 0.06 mm² in 45-nm CMOS.

In this paper, a technique for slew-rate (SR) boosting suitable for switched-capacitor circuits is proposed. The proposed technique makes use of a class-B auxiliary amplifier that generates a compensating current only when high SR is demanded by large signals. The proposed architecture employs simple circuitry to detect the need for a large output current by employing a highly sensitive pre-amplifier followed by a class-B amplifier. The functionality of the class-B transconductance amplifier is dictated by a predefined hysteresis, and operates in parallel with the main amplifier. The proposed solution demands small static power (under 20% of main amplifier power) due to its class-B nature. The experimental results in a 40-nm CMOS technology show more than 45% reduction in slew time, and a 28% shorter slew time for 1% settling time when used in a typical 4.5 bit/stage block commonly used in pipelined analog-to-digital converters. Compared with the core amplifier, HD3 at 500 MHz reduces by more than 10 dB when the SR boosting circuit is activated.

This paper revises the recent design trends of linear low-dropout regulators. The design issues and advantages of analog LDOs (ALDO) are discussed. High-performance operation and high rejection to supply noise when delivering large current values is a major advantage of the ALDO, but transient response when transitioning from standby operation to full load is a major issue; the main limitation is the slow charging/discharging of the large gate’s capacitor of the pass transistor. This issue is more critical when designing full-on chip ALDOs, where large load capacitors are not available. Digital LDOs (DLDO) employ digital controllers that drive the segmented pass transistor, in most of the cases operate in triode region. The digital nature of the DLDO scales with the technology, but its rejection to supply noise is limited. Mixed-mode LDOs take advantage of the properties of both ALDO and DLDOs. Transient is managed by the agile DLDO and steady state operation is mainly handled by the clock glitch free ALDO. In this paper, all three architectures are revisited.

This paper deals with the design of low-power high-performance continuous-time filters. The proposed operational transconductance amplifier architecture employs current-reuse differential difference amplifiers in order to produce more power-efficient G _m -C filter solutions. To demonstrate this, a sixth-order low-pass Butterworth filter was designed in a 0.18-μm CMOS, achieving a 65-MHz -3-dB frequency, an in-band input-referred third-order intercept point of 12 dBm, and an input-referred noise density of 40 nV/Hz ^1/2 , while only consuming 8.07 mW from a 1.8-V supply and occupying a total chip area of 0.21 mm ² with a power consumption of only 1.19 mW per pole.

A pipeline analog-to-digital converter (ADC) with high power efficiency is implemented in this paper. The ADC architecture consists of 3.5b, 3.5b, 3.5b, and 4b sub-ADCs. For the first three stages, a current-reuse technique is employed in the current mode multiplying digital-to-analog converters (MDACs). An operational transconductance amplifier (OTA) converts an input voltage into current; A current-steering DAC reuses the OTA bias current. The OTA and the DAC generate the sub-ADC residue in a current domain. As a result, both power consumption and thermal noise for the MDAC are reduced. A transimpedance amplifier (TIA) with a feedback resistor is utilized to convert the current signal to a voltage residue signal for the next stage. An off-chip calibration scheme is used to correct interstage gain and nonlinearity errors. The fabricated ADC achieves 68.1 dB signal-to-noise-and-distortion ratio (SNDR) and 82.3 dB spurious free dynamic range (SFDR) for a sinusoidal input at 4.17 MHz. The ADC operates at a maximum sampling frequency of 260 MHz. With an input signal at 123.129 MHz, the measured SNDR/SFDR are 66.3/78.22 dB, respectively. The total power consumption for the ADC running at maximum speed is 15.38 mW. Thus, the pipeline ADC achieves a 167.4 dB figure-of-merit (FoM). The chip was manufactured in a TSMC 40-nm CMOS process.