This article introduces an accurate current-mode bandgap reference circuit design with a novel shared offset compensation scheme for its internal amplifiers. This bandgap circuit has been designed to operate over a very wide temperature range from -40 °C to 150 °C. Its output voltage is 1.16 V with a 3.3-V supply voltage. A multi-section curvature compensation method alleviates the error from the bipolar junction transistor's base-emitter nonlinear voltage dependence on temperature. The bandgap reference circuit contains two operational amplifiers that are utilized to generate proportional-to-absolute-temperature (PTAT) and complementary-to-absolute-temperature (CTAT) current sources. With the implementation of the described shared offset-cancellation methodology, the simulated output inaccuracy introduced by the amplifier is kept to a 5σ offset within ±4.6 μV while allowing to conserve die size and power consumption by preventing that each amplifier is accompanied by its own active auxiliary offset-cancellation circuit. Designed and fabricated in a 130-nm CMOS process technology, the bandgap reference has a measured output voltage shift of less than 1 mV over a -40 °C to 150 °C temperature range and an overall variation of ±8.2 mV across seven measured samples without trimming.

A major obstacle during the design of brain- computer interfaces is the unavailability of a neural implantable device that is μ-scale in size and is wireless, self-powered, and long-lasting. The current state-of-the-art implantable devices suffer from various limitations. Electromagnetic-based wireless devices are big in size because of their large antenna, which must be larger than one-tenth of the wavelength of the operational frequency. Ultrasound-based wireless devices, in addition to their low data rate, have massive loss in the skull and need an intermediate electromagnetic transceiver under the skull. Furthermore, almost all state-of-the-art wireless devices use micro-electrodes for neuronal recording, which are not reliable in long-term monitoring applications because of the direct contact between the tissue and metal electrodes. In this paper, we propose a novel, wireless, and ultra-compact implantable device termed NanoNeuroRFID. At the core of this device, there is a magnetoelectric (ME) antenna array. ME antennas are smart and ultra-miniaturized (<;200 μm diameter) and can perform multiple tasks. First, can harvest electromagnetic energy to power the NanoNeuroRFID system. Their limit of the detection for RF magnetic fields is 40 pT; second, they can sense quasi-static neuronal magnetic fields as small as 200 pT without direct contact to the tissue, allowing a long lifetime and reliable neural recording; and third, they can communicate with an external transceiver, and their operational frequency could be 10 to 100 s of MHz, where tissue loss is small.

This paper demonstrates an input impedance boosting method that was developed for long-term monitoring of electroencephalography signals. An instrumentation amplifier was designed with a negative capacitance generation feedback (NCGFB) technique to cancel the adverse effects of input capacitances from electrode cables and printed circuit boards. The NCGFB boosts the measured impedance from below 40 MΩ to above 500 MQ at 50 Hz when the equivalent capacitance at the inputs is up to 150 pF. The prototype chip includes an automatic calibration system to adaptively enhance the input impedance through on-chip test signal generation, measurement, and the automatic digital control of the NCGFB. Consisting of an instrumentation amplifier, a low-pass notch filter, and a variable gain amplifier in 130-nm CMOS technology, the signal path has a combined gain range of 66-93 dB with a total power consumption of 42 μW. The front-end bandwidth covers 0.5-48 Hz, and its integrated input-referred noise over the bandwidth is 3.75 μV _rms . The measured third-order harmonic distortion component is at least 57 dB below the fundamental signal level. A common-mode rejection ratio of 77.6 dB and a power supply rejection ratio of 74 dB were measured at 10 Hz. When activated, the auxiliary test signal generation and calibration circuits consume a power of 542 μW.

This paper introduces a continuous-time low-pass sigma-delta modulator operating with a seven-phase 400 MHz clocking scheme to control time-based processing in the 3-bit two-step quantizer and main digital-to-analog converter (DAC). An on-chip voltage-controlled oscillator and a complementary injection-locked frequency divider are utilized for low-jitter clock signal generation with multiple phases, allowing 3-bit pulse-width modulated feedback with a single-element DAC to avoid performance degradation from unit element mismatch problems associated with conventional multi-bit DACs. Fabricated in a standard 0.18 μm CMOS technology, the 5th-order modulator achieves a peak SNDR of 67.7 dB in 25 MHz bandwidth, consumes 48 mW from a 1.8 V supply, and occupies a die area of 2.6 mm ² . The modulator has a measured SFDR of 78 dB and in-band IM3 under -72 dB with -2 dBFS two-tone signal power.

This article presents a fully integrated RF energy harvester (EH) with 30% end-to-end power harvesting efficiency (PHE) and supports high-output voltage operation, up to 9.3 V, with a 1.07-GHz input and under the electrode model for neural applications. The EH is composed of a novel ten-stage self-biased gate (SBG) rectifier with an on-chip matching network (MN). The SBG topology elevates the gate-bias of transistors in a nonlinear manner to enable higher conductivity. The design also achieves $>$ 20% PHE range of 12 dB. The design was fabricated in 65-nm CMOS technology and occupies an area of 0.0732 mm2 with on-chip MN. In addition to standalone EH characterization measurement results, animal tissue stimulation test was performed to evaluate its performance in a realistic neural implant application.

This article reviews design challenges for low-power CMOS high-speed analog-to-digital converters (ADCs). Basic ADC converter architectures (flash ADCs, interpolating and folding ADCs, subranging and two-step ADCs, pipelined ADCs, successive approximation ADCs) are described with particular focus on their suitability for the construction of power-efficient hybrid ADCs. The overview includes discussions of channel offsets and gain mismatches, timing skews, channel bandwidth mismatches, and other considerations for low-power hybrid ADC design. As an example, a hybrid ADC architecture is introduced for applications requiring 1 GS/s with 6–8 bit resolution and power consumption below 11 mW. The hybrid ADC was fabricated in 130-nm CMOS technology, and has a subranging architecture with a 3-bit flash ADC as a first stage, and a 5-bit four-channel time-interleaved comparator-based asynchronous binary search (CABS) ADC as a second stage. Testing considerations and chip measurements results are summarized to demonstrate its low-power characteristics.