An off-board dc fast battery charger for electric vehicles (EVs) with an original control strategy aimed to provide ripple-free output current in the typical EV batteries voltage range is presented in this article. The proposed configuration is based on modular three-phase interleaved converters and supplied by the low-voltage ac grid. The ac/dc interleaved three-phase active rectifier is composed of three standard two-level three-phase converter modules with a possibility to slightly adjust the dc-link voltage level in order to null the output current ripple. A modular interleaved dc/dc converter, formed by the same three-phase converter modules connected in parallel, is used as an interface between the dc link and the battery. The use of low-cost, standard and industry-recognized three-phase power modules for high-power fast EV charging stations enables the reduction of capital and maintenance costs of the charging facilities. The effect of coupling on the individual input/output inductors and total input/output current ripples has been investigated as well, considering both possible coupling implementations, i.e., inverse and direct coupling. Numerical simulations are reported to confirm the feasibility and the effectiveness of the whole EV fast charging configuration, including the proposed control strategy aimed to null the ripple of the output current. Experimental results are provided by a reduced scale prototype of the output stage to verify the ripple-free output current operation capability.

The three-phase voltage source inverter (VSI) is de facto standard in power conversion systems. To realize high power density systems, one of the items to be correctly addressed is the design and selection of the dc-link capacitor in relation to the voltage switching ripple. In this paper, effective formulas for designing the dc-link capacitor as a function of the switching voltage ripple amplitude are obtained, considering the operating conditions such as the modulation index and the output current amplitude. The calculations are obtained considering the requirements and restrictions referring to the high (switching)-frequency dc-link voltage ripple component. Analyses have been performed considering the dc source impedance (non-ideal dc voltage source at the switching frequency) and a balanced load. Analytical expressions are derived for the dc-link voltage switching ripple amplitude and its maximum value over the fundamental period. Different values of modulation index and output phase angle have been considered and different diagrams are presented. Analytical results were validated both by simulations and comprehensive experimental tests.

This paper presents a generalized approach towards the dc-link voltage switching ripple analysis in two-level multiphase PWM voltage source inverters with balanced load. Since voltage ripple is one of the crucial sizing criteria for dc-link capacitor, simple and practical equation for designing the dc-link capacitor based on the maximum (peak-to-peak) value of the dc-link voltage ripple has been proposed for multiphase inverters. The amplitude of the dc-link voltage switching ripple is analytically derived as a function of operating conditions. The effect of the number of phases on the dc-link capacitor size is investigated as well. It is found that considering the same total output current, the dc-link capacitor size is reduced increasing the number of phases up to seven. However, from the point of view of dc-link capacitor size, there are no benefits of further increasing the number of phases. Reference is made to two commonly used modulation strategies – sinusoidal PWM and continuous symmetric centered PWM (i.e., space vector). The mathematical models derived aim to provide precise dc-link capacitor sizing and hence improve the power density of the whole system. Comparison within different phase numbers has been made. Proposed theoretical developments are verified by simulations and experimental tests.

Direct current (DC)-link voltage ripple analysis is essential for determining harmonic noise and for DC-link capacitor design and selection in single-phase pulse-width modulation (PWM) inverters. This paper provides an extensive theoretical analysis of DC-link voltage ripple for full-bridge (H-bridge) inverters, with simulation and experimental verifications, considering a DC source impedance (non-ideal DC voltage source). The DC voltage ripple amplitude is theoretically estimated as a function of the output current, both amplitude and phase angle, and the modulation index. It consists of a switching frequency component and a double-fundamental frequency component (i.e., 100 Hz), thereby both components are considered in the analysis. In particular, the peak-to-peak distribution, maximum amplitude, and root mean square (RMS) values of the voltage switching ripple over the fundamental period are obtained. Based on the DC voltage requirements, simple and effective guidelines for designing DC-link capacitors are obtained.

Inverter's performance and operating mode may be negatively affected by inverter input (dc‐link) current and voltage ripple. It is a common experience that even theoretically balanced loads with perfectly balanced supply voltages, such as multiphase ac motors supplied by pulse‐width modulation (PWM) inverters, in practice show a certain degree of current unbalance, in the range of a few percent, which introduces a low‐frequency instantaneous power oscillation. This reflects in current and voltage low‐frequency ripple on the dc‐link inverter side (i.e. at the double‐fundamental frequency). A possible method to analyse this matter is through the symmetric sequence components. In particular, based on the first negative current sequence component and by considering the equivalent dc‐link impedance calculated at the dominant double‐fundamental frequency, the amplitude of the corresponding dc‐link voltage ripple component is calculated in this work for a general multiphase load. Finally, the design of the dc‐link capacitor in multiphase inverters is proposed considering requirements referred to the double‐fundamental dc voltage ripple. The feasibility of the proposed developments has been verified for three‐, five‐ and seven‐phase inverters by both numerical simulations and comprehensive experimental tests, always showing a good matching.

This paper presents the analysis of the DC‐link voltage switching ripple in five‐phase PWM voltage source inverters with balanced load. The analysis is particularly important for the design and selection of a DC‐link capacitor making it possible to meet desired electrical performance of the inverter system. Simple and practical equation for designing the DC‐link capacitor is proposed relating the value of capacitance to the maximum value (peak‐to‐peak) of the DC‐link voltage ripple. The amplitude of the DC‐link voltage switching ripple is analytically derived as a function of modulation index, and the amplitude of the output current and phase angle. In order to show peak‐to‐peak voltage ripple distribution, different diagrams are introduced. Reference is made to continuous symmetric centred PWM modulation (i.e., space vector modulation SVM). In order to verify proposed developments, simulations have been carried out by Matlab/Simulink considering full range of modulation index and output phase angle.