In this paper, we reviewed the recent trends on neuromorphic computing using emerging memory technologies. Two representative learning algorithms used to implement a hardware-based neural network are described as a bio-inspired learning algorithm and software-based learning algorithm, in particular back-propagation. The requirements of the synaptic device to apply each algorithm were analyzed. Then, we reviewed the research trends of synaptic devices to implement an artificial neural network.

A reconfigurable field-effect transistor (RFET) with memory functionality is proposed as a new high-density synaptic device capable of exclusive NOR (XNOR) operation for a binary neural network (BNN). A RFET with three gates is used in this letter, consisting of two program gates (PGs) electrically connected to each other and a control gate (CG) between the PGs. By changing the polarity of the PG bias or the polarity of the charge trapped in Si ₃ N ₄ layer on the PGs, the RFET operates as an nor a p-MOSFET having a CG as a switching gate. The XNOR operation is successfully demonstrated in a fabricated RFET. The on/off current ratio (the ratio of 1 to 0 in the result of the XNOR operation) is ~10 ⁴ and the current is ~1 nA/μm. Using a RFET as a synaptic device for a BNN is efficient in terms of the area (~8F ² /synapse) because XNOR operation can be performed using only one RFET.

Ca-doped Na⁺- β/β^′′-alumina was synthesized using a solid-state reaction. The changes in the properties of Na⁺- β/β^′′-alumina resulting from the presence of Ca impurity were studied. Ca (0–5 wt%) was added to the respective samples, which were then sintered. The specimens were characterized using X-ray diffraction, scanning electron microscopy, densimetry and impedance analysis. In the sintered specimens, the β^′′-alumina phase fraction decreased as Ca content increased, whereas the relative sintered density increased. The surface morphology of Ca-doped Na⁺- β/β^′′-alumina specimens showed a Ca-rich layer, which was the main cause of increase in the specific resistance.

The pursuit of sub‐1‐nm field‐effect transistor (FET) channels within 3D semiconducting crystals faces challenges due to diminished gate electrostatics and increased charge carrier scattering. 2D semiconductors, exemplified by transition metal dichalcogenides, provide a promising alternative. However, the non‐idealities, such as excess low‐frequency noise (LFN) in 2D FETs, present substantial hurdles to their realization and commercialization. In this study, ideal LFN characteristics in monolayer MoS₂ FETs are attained by engineering the metal‐2D semiconductor contact and the subgap density of states (DOS). By probing non‐ideal contact resistance effects using CuS and Au electrodes, it is uncovered that excess contact noise in the high drain current (I_D) region can be substantially reduced by forming a van der Waals junction with CuS electrodes. Furthermore, thermal annealing effectively mitigates sulfur vacancy‐induced subgap density of states (DOS), diminishing excess noise in the low I_D region. Through meticulous optimization of metal‐2D semiconductor contacts and subgap DOS, alignment of 1/f noise with the pure carrier number fluctuation model is achieved, ultimately achieving the sought‐after ideal LFN behavior in monolayer MoS₂ FETs. This study underscores the necessity of refining excess noise, heralding improved performance and reliability of 2D electronic devices.