We present a novel ultrathin avalanche photodiode (APD) with a silicon (Si) body thickness of 640 nm and optimized doping profiles to significantly improve the detection efficiency in ultraviolet (UV) spectral range from near UV (NUV) to UV-C (here studied down to 275 nm). The square photodiode is fabricated on silicon-on-insulator (SOI) substrate with an active area of 420 μm² (37 μm x 37 μm) consisting of n⁺⁺/p-well and an n-well guard ring (GR). The dark current-voltage (I-V) characteristic exhibits low leakage current (≈pA) and breakdown voltage of 8.6 V. A peak quantum efficiency (QE) of 93.88% is obtained on a wavelength of 400 nm at 4 V. An outstanding expansion of the sensitivity in UV-C is presented with a QE of 82.75% under a wavelength of 275 nm at 4 V. With a gain value of 4.9, a responsivity of 14.46 A/W at a wavelength of 400 nm on a low-level light intensity of 3.28 μW/cm² is achieved at 7.8 V. A sufficient detection performance in visible spectral range has also been achieved due to the formation of the sandwiched thin silicon body between nearly 200-nm SiO₂ on top and 1-μm buried SiO₂ (BOX). This proposed ultrathin photodiode indicates a potential high avalanche gain (>10⁵) in Geiger mode.

This work investigates the robustness of an ultrathin backside-illuminated (BSI) silicon-on-insulator (SOI) single-photon avalanche diode (SPAD) against gamma-ray irradiation for space applications. Experimental results demonstrate a breakdown voltage shift in the studied SPAD from 10.17 to 9.95 V after a total ionizing dose (TID) of 132 krad(Si). An increase in dark count rate (DCR) from 1490 to 2700 cps/μm² at 1 V excess bias is shown at this dose. TCAD simulations explain the role of the oxide-trapped charges, induced by irradiation in the insulating layer surrounding the active region, on the SPAD performance. These trapped charges shift the peak electric field, leading to premature breakdown while the extension of the active area affected by impact ionization increases the DCR. Further simulations show that implementing a perimeter-gated structure and reducing oxide thickness can effectively mitigate these effects by leveraging capacitive effects, preventing a breakdown voltage shift. The perimeter gate (PG) lowers the simulated DCR after irradiation from 2700 to 1365 cps/μm², thereby enhancing the radiation resilience of ultrathin SOI SPADs beyond a TID of 132 krad(Si).

The realization of 30 µm-deep trench isolation in a linear array of butt-coupled 3D CMOS silicon photodetectors is investigated by implementing the formation of a shallow n⁺-p junction and SiO₂-liner over the trench sidewalls as well as the SU-8 filling trenches for passivation. The dependency of the dark I-V curve on the trench isolation scheme is analyzed by monitoring the dynamic dark I-V measurements of four samples including the schemes of single-trench isolation with different widths and the scheme of double-trench isolation. The highest and the lowest dark currents are measured in the detectors with the widest single-trench isolation and the double-trench isolation, respectively.

Silicon membrane strip photodetectors are fabricated based on thin silicon-on-insulator (SOI) wafers. The thin SOI wafer is realized by exploiting a thinning process on backside. Such detectors can be implemented in proton-beam position detection because its ultra-thin membrane substrate can reduce beam scattering and offer the considerable advantages of higher radiation hardness. A p-spray implantation process is typically performed at the silicon surface between the ${\mathrm{n}}^{+}$ -strips in order to insulate them, without requiring an extra photolithographic mask. In this paper, the sources of leakage current in the detector are first studied by considering both activation energy and simulation analysis in Silvaco TCAD. While the device is operating below avalanche breakdown voltage, the Shockley–Read–Hall process and trap-assisted-tunneling process are dominantly contributing to leakage current. The dominant breakdown voltage is attributed to the premature breakdown in the junction of ${\mathrm{p}-\mathrm{spray}/\mathrm{n}}^{+}$ region. The shift of this breakdown voltage under repeated avalanche processes is analyzed in-depth by both experiments and simulations, as a function of temperature and electrical stress conditions, which are introducing an important reliability problem. The electrical stress can be attributed to an increase in fixed charge density at the Si/${\mathrm{SiO}}_2$ interface. The breakdown voltage finally increases by 4 V after successive avalanche breakdowns as a function of the applied excess bias voltage beyond breakdown voltage.