Integration of graphene with Si microelectronics is very appealing by offering a potentially broad range of new functionalities. New materials to be integrated with the Si platform must conform to stringent purity standards. Here, we investigate graphene layers grown on copper foils by chemical vapor deposition and transferred to silicon wafers by wet etching and electrochemical delamination methods with respect to residual submonolayer metallic contaminations. Regardless of the transfer method and associated cleaning scheme, time-of-flight secondary ion mass spectrometry and total reflection X-ray fluorescence measurements indicate that the graphene sheets are contaminated with residual metals (copper, iron) with a concentration exceeding 10¹³ atoms/cm². These metal impurities appear to be partially mobile upon thermal treatment, as shown by depth profiling and reduction of the minority charge carrier diffusion length in the silicon substrate. As residual metallic impurities can significantly alter electronic and electrochemical properties of graphene and can severely impede the process of integration with silicon microelectronics, these results reveal that further progress in synthesis, handling, and cleaning of graphene is required to advance electronic and optoelectronic applications.

Back-end-of-line integrated 1 × μm ² TiN/HfO ₂ /Ti/TiN MIM memory devices in a 0.25- μm complementary metal-oxide-semiconductor technology were built to investigate the conduction mechanism and the resistive switching behavior as a function of temperature. The temperature-dependent I - V characteristics in fresh devices are attributed to the Poole-Frenkel mechanism with an extracted trap energy level at φ ≈ 0.2 eV below the HfO ₂ conduction band. The trap level is associated with positively charged oxygen vacancies. The electroformed memory cells show a stable bipolar switching behavior in the temperature range from 213-413 K. The off -state current increases with temperature, whereas the on-state current can be described by a weak metallic behavior. Furthermore, the results suggest that the I - V cycling not only induces significant changes in the electrical properties of the MIM memory devices, i.e., the increase in the off-state current, but also stronger temperature dependence. The temperature effect on the on-state and off-state characteristics is modeled within the framework of the quantum point-contact model for dielectric breakdown using an effective temperature-dependent confinement potential.

A physics-based analytical model for the current-voltage (I-V) characteristics corresponding to the low and high resistive states in electroformed metal-insulator-metal structures with HfO ₂ layers is proposed. The model relies on the Landauer theory for the electron transport in mesoscopic systems. The switching phenomenon is ascribed to the modulation of the constriction's bottleneck cross-sectional area associated with atomic rearrangements within the confinement path. The extracted parameter values allow one to conclude that the length and radius of the region that controls the conduction characteristics are in the nanometer range.

Resistive switching memory (RRAM) is a promising technology for embedded memory and its application in computing. In particular, RRAM arrays can provide a convenient primitive for matrix-vector multiplication (MVM) with strong impact on the acceleration of neural networks for artificial intelligence (AI). At the same time, RRAM is affected by intrinsic conductance variations, which might cause degradation of accuracy in AI inference hardware. This work provides a detailed study of the multilevel-cell (MLC) programming of RRAM for neural network applications. We compare three MLC programming schemes and discuss their variations in terms of the different slopes in the programming characteristics. We test the accuracy of a two-layer fully connected neural network (FC-NN) as a function of the MLC scheme, the number of weight levels, and the weight mapping configuration. We find a tradeoff between the FC-NN accuracy, size, and current consumption. This work highlights the importance of a holistic approach to AI accelerators encompassing the device properties, the overall circuit performance, and the AI application specifications.

We have analyzed the strain distribution and the photoluminescence in Ge microstructures fabricated by means of a Si-CMOS compatible method. The tensile strain in the Ge microstructures is obtained by using a SiN stressor layer. Different shapes of microstructure, allowing the Ge layers to freely expand into one, two, or three dimensions, resulted in different strain distribution profiles. Maximal equivalent biaxial tensile strain values up to ∼0.8% have been measured. Room temperature photoluminescence emission has been observed and attributed to direct-band gap recombination spectrally shifted by tensile strain.