A research of total ionizing dose and annealing effects on Schottky type p-GaN gate Al0.2Ga0.8N/GaN high electron mobility transistors (HEMTs) has been carried out. Devices with breakdown voltages of 100V/200V/650V were irradiated under Co-60 X-rays. Radiation doses reach to a total amount of 500 krad (Si) with dose rate of 50 rad(Si)/s under gate biases of ${V}_{GS}=0\text{V}$ /+3V/+5V. Negative threshold voltage shifts were observed, especially under positive gate biases. It is found out that the threshold voltage shifts are due to the accumulation of positive charges (holes) trapped in the interface of p-GaN/AlGaN. Therefore, the shift amount is proportional to the gate bias and the radiation amount, while not related to the breakdown voltage. After the total ionizing dose experiments, both high temperature and room temperature annealing processes were taken. During the annealing processes, the shifted threshold voltage recovered, and high temperature accelerated the recovery process. Experiment results indicate that the total ionizing dose effect is recoverable.

In this article, a recessed source trench silicon carbide (SiC) MOSFET with integrated MOS-channel diode (MCD) is proposed and investigated by TCAD simulations. The MCD features a short channel, and the channel length could be adjusted by varying the recessed depth. Owing to the drain-induced barrier lowering effect, a low potential barrier for electrons to flow through the JFET region to the N $+$ source region is formed, which successfully eliminates the bipolar degradation of the parasitic body p-i-n diode. Besides, the recessed source trench introduces an additional depletion region and homogenizes the distribution of the OFF-state electric field. As a result, a low gate-to-drain capacitance and a high breakdown voltage (BV) are obtained. Simulation results indicate that compared with the SiC trench MOSFET with integrated self-assembled three-level protection Schottky barrier diode, a 78.7% reduction in gate-to-drain capacitance and a 24.4% improvement in BV could be achieved in the proposed SiC MOSFET.

A research on time-resolved threshold voltage instability of 650-V Schottky type p-GaN gate Al _0.2 Ga _0.8 N/GaN high electron mobility transistor (HEMT) under high-temperature gate bias (HTGB) conditions has been carried out. Both forward and reverse bias conditions are applied. We found that the threshold voltage of p-GaN AlGaN/GaN HEMT shifts negatively under high-temperature forward gate bias (HTFB), while shifts positively under high-temperature reverse gate bias (HTRB). Negative threshold voltage shifts under forward gate bias are largely due to the trapped positive charges (holes) caused by existing defects in the AlGaN layer. The holes are from the accumulated 2-D hole gas (2DHG) in the p-GaN layer near the p-GaN/AlGaN interface, which may be partially filled into the AlGaN layer by tunneling effect. Therefore, negative threshold voltage shifts under HTFB are temperature-independent. Positive threshold voltage shifts under reverse gate bias are from the hole emission in the p-GaN layer and the trapped negative charges (electrons) in the AlGaN layer. The electrons are trapped by defects resulted from the created hot holes in high temperature. The positive threshold voltage shift under HTRB is temperature-dependent, where higher temperature leads to a larger positive threshold voltage shift.

A novel p-GaN gate AlGaN/GaN high electron mobility transistor (HEMT) structure with a stepped hybrid GaN/AlN buffer layer (S-HEMT) is proposed and simulated by the Sentaurus TCAD in this paper. A stepped hybrid GaN/AlN buffer layer is adopted and the step is near the interface of the gate and drain. First, the breakdown voltage ( BV ) of the proposed S-HEMT is significantly improved with the introduction of a stepped hybrid GaN/AlN buffer layer, which can effectively modulate the electric field distributions along the channel. Second, the AlN buffer layer below the stepped GaN buffer has a large band offset and a strong polarization, which results in a much lower leakage current and a better carrier confinement. Consequently, the BV of the proposed S-HEMT will be improved at no expense of the specific on-resistance ( ${R} _{\mathrm{ on,sp}}$ ). Compared with those of the conventional p-GaN gate AlGaN/GaN HEMT on the same gate-to-drain distance of $12 ~\mu \text{m}$ , a higher BV of 1781 V and FOM of 0.72 GW/cm ² are obtained for the proposed S-HEMT, which are both about five times. The proposed S-HEMT exhibits the potential and advantage in high power electronic applications.

A novel segmented laterally diffused MOS embedded silicon-controlled rectifier (SCR) structure, called NSLDMOS-SCR, is proposed and verified in an optimal 5-V/40-V bipolar CMOS DMOS (BCD) process. Superior to the strip LDMOS-SCR, the proposed NSLDMOS-SCR exhibits a high holding voltage of 20.6 V and an excellent failure current of 12.2 A in a width of 200 $\mu$ m, benefitting from the widened segmented topology of the source and body. As such, for $\pm$ 15-V circuit application, the NSLDMOS-SCR can fit the electrostatic discharge (ESD) design window for an eight-channel CMOS analog multiplexer and effectively protect these pins against 8-kV human-body-mode ESD stress.

In this article, a 1200-V asymmetric trench (AT) silicon carbide (SiC) metal–oxide–semiconductor field effect transistor (MOSFET) with an integrated junction field effect transistor (JFET) is proposed with improved cut-in voltage ( $\textit{V}_{\text{cut-in}}$ ) and switching loss. For the proposed device named IJ-ATMOS, the bottom p-well in contact with the source can deplete the surrounding current spreading layer (CSL) region, so the JFET channel (JFET-C) is normally-OFF when device is in forward operation. In addition, the source is in contact with CSL. Due to a smaller potential barrier, $\textit{V}_{\text{cut-in}}$ of this path is lower than the p-n body diode. Therefore, the intrinsic body diode is fully inactivated and the bipolar degradation is eliminated. Meanwhile, the gate to drain charge ( $\textit{Q}_{\text{gd}}$ ) and switching loss are reduced by using the split gate MOSFET structure. Through TCAD simulation, the IJ-ATMOS decreases $\textit{V}_{\text{cut-in}}$ by 50.35% compared to the conventional AT SiC MOSFET (C-ATMOS). The $\textit{Q}_{\text{gd}}$ and the switching loss are decreased by 14.29% and 30.61%, respectively. $^{^{^{}}}$