In this article, a 1200-V asymmetric trench (AT) silicon carbide (SiC) metal–oxide–semiconductor field effect transistor (MOSFET) with an integrated junction field effect transistor (JFET) is proposed with improved cut-in voltage ( $\textit{V}_{\text{cut-in}}$ ) and switching loss. For the proposed device named IJ-ATMOS, the bottom p-well in contact with the source can deplete the surrounding current spreading layer (CSL) region, so the JFET channel (JFET-C) is normally-OFF when device is in forward operation. In addition, the source is in contact with CSL. Due to a smaller potential barrier, $\textit{V}_{\text{cut-in}}$ of this path is lower than the p-n body diode. Therefore, the intrinsic body diode is fully inactivated and the bipolar degradation is eliminated. Meanwhile, the gate to drain charge ( $\textit{Q}_{\text{gd}}$ ) and switching loss are reduced by using the split gate MOSFET structure. Through TCAD simulation, the IJ-ATMOS decreases $\textit{V}_{\text{cut-in}}$ by 50.35% compared to the conventional AT SiC MOSFET (C-ATMOS). The $\textit{Q}_{\text{gd}}$ and the switching loss are decreased by 14.29% and 30.61%, respectively. $^{^{^{}}}$

Threshold voltage ( V _TH ) degradation mechanisms induced by the ionizing irradiation for the 1200V double trench (DT) SiC MOSFET are investigated. The ionizing irradiation experiment is performed with different gate-source voltages ( V _GS ) and total ionizing doses (TID). The maximum V _TH shifts are -1.92 V for V _GS of 0 V and TID of 500 krad(Si), and -4.73 V for V _GS of 20 V and TID of 150 krad(Si), respectively. A novel method of investigation on TID-induced V _TH shift from energy domain and numerical simulation with the aid of the TCAD tool is exploited. Extensive simulations indicate that donor-like oxide traps with energy larger than 0.55 eV dominate the negative V _TH shift. The summation of two Gaussian distribution models is used to emulate trapped hole energy distribution, the relative errors between measured and simulated V _TH shifts are within ±13.36% at TID of 100 krad(Si).

The single-event effect reliability issue is one of the most critical concerns in the context of space applications for SiC VDMOS. In this paper, the SEE characteristics and mechanisms of the proposed deep trench gate superjunction (DTSJ), conventional trench gate superjunction (CTSJ), conventional trench gate (CT), and conventional planar gate (CT) SiC VDMOS are comprehensively analyzed and simulated. Extensive simulations demonstrate the maximum SET current peaks of DTSJ−, CTSJ−, CT−, and CP SiC VDMOS, which are 188 mA, 218 mA, 242 mA, and 255 mA, with a bias voltage V_DS of 300 V and LET = 120 MeV·cm²/mg, respectively. The total charges of DTSJ−, CTSJ−, CT−, and CP SiC VDMOS collected at the drain are 320 pC, 1100 pC, 885 pC, and 567 pC, respectively. A definition and calculation of the charge enhancement factor (CEF) are proposed. The CEF values of DTSJ−, CTSJ−, CT−, and CP SiC VDMOS are 43, 160, 117, and 55, respectively. Compared with CTSJ−, CT−, and CP SiC VDMOS, the total charge and CEF of the DTSJ SiC VDMOS are reduced by 70.9%, 62.4%, 43.6% and 73.1%, 63.2%, and 21.8%, respectively. The maximum SET lattice temperature of the DTSJ SiC VDMOS is less than 2823 K under the wide operating conditions of a drain bias voltage V_DS ranging from 100 V to 1100 V and a LET value ranging from 1 MeV·cm²/mg to 120 MeV·cm²/mg, while the maximum SET lattice temperatures of the other three SiC VDMOS significantly exceed 3100 K. The SEGR LET thresholds of DTSJ−, CTSJ−, CT−, and CP SiC VDMOS are approximately 100 MeV·cm²/mg, 15 MeV·cm²/mg, 15 MeV·cm²/mg, and 60 MeV·cm²/mg, respectively, while the value of V_DS = 1100 V.

Single-event gate-rupture (SEGR) in the trench vertical double-diffused power MOSFET (VDMOS) occurs at a critical bias voltage during heavy-ion experiments. Fault analysis demonstrates that the hot spot is located at the termination of the VDMOS, and the gate oxide in the termination region has been damaged. The SEGR-hardened termination with multiple implantation regions is proposed and simulated using the Sentaurus TCAD. The multiple implantation regions are introduced, leading to an increase in the distance between the gate oxide and the hole accumulation region, as well as a decrease in the resistivity of the hole conductive path. This approach is effective in reducing the electric field of the gate oxide to below the calculated critical field, and results in a lower electric field than the conventional termination.

In this paper, a novel asymmetric trench SiC MOSFET with a Poly-Si/SiC heterojunction diode (HJD-ATMOS) is designed to improve its reverse conduction characteristics and switching performance. This structure features an integrated heterojunction diode, which improves body diode characteristics without affecting device static characteristics. The heterojunction diode acts as a freewheeling diode during reverse conduction, reducing the cut-in voltage (V_cut-in) to a lower level than conventional asymmetric trench SiC MOSFET (C-ATMOS), while maintaining a similar breakdown voltage. Meanwhile, the split gate structure reduces gate-to-drain charge (Q_gd). Through TCAD simulation, the HJD-ATMOS decreases V_cut-in by 53.04% compared to the C-ATMOS. Both Q_gd and switching loss are reduced, with a decrease of 31.91% in Q_gd and 40.29% in switching loss.

In this paper, the resistance degradation behaviors of double trench (DT) and asymmetric trench (AT) SiC MOSFETs under total ionizing dose (TID) effect and high drain voltage bias are investigated in detail. The output characteristics measurement results before and after irradiation indicate that the TID effect with high drain voltage bias increases the drain current, resulting in the On-state resistance degradation, whereas the high drain voltage bias seems to have no impact on the degradation. In particular, the DT SiC MOSFETs demonstrate a greater degree of degradation in comparison to the AT SiC MOSFETs under the same gate voltage. This phenomenon can be attributed to a more pronounced decline in channel resistance. Simultaneously, the threshold voltage ( V _TH ), the drain leakage current ( I _DSS ), and the gate leakage current ( I _GSS ) are also measured, which can be concluded that the resistance degradation is attributable to the V _TH negative shifting induced by the positive charge accumulation in the gate oxide. Furthermore, the AT SiC MOSFETs have better irradiation tolerance owing to the P-shield asymmetric trench structure, exhibiting slight shift in the V _TH , the I _DSS , and the I _GSS . Finally, the TCAD simulations are utilized to successfully verify the degradation mechanism.