We report a general strategy for obtaining high-quality, large-area metal-chalcogenide semiconductor films from precursors combining chelated metal salts with chalcoureas or chalcoamides. Using conventional organic solvents, such precursors enable the expeditious formation of chalco-gels, which are easily transformed into the corresponding high-performance metal-chalcogenide thin films with large, uniform areas. Diverse metal chalcogenides and their alloys (MQ_x: M = Zn, Cd, In, Sb, Pb; Q = S, Se, Te) are successfully synthesized at relatively low processing temperatures (10⁷ and good operational stability (threshold voltage shift < 0.5 V at a positive gate bias stress of 10 ks). In addition, metal chalcogenide–based phototransistors with a photodetectivity of >10¹³ Jones and seven-stage ring oscillators operating at a speed of ~2.6 MHz (propagation delay of < 27 ns per stage) are demonstrated.

Oxide semiconductor thin‐film transistors (TFTs) with low‐voltage operation, excellent device performance, and bias stability are highly desirable for portable and wearable electronics. Here, the development of low‐voltage indium‐tin‐zinc‐oxide (ITZO) TFTs with excellent device performance and bias stability based on a dual‐channel layer and an anodic‐oxide dielectric layer are reported. An ultra‐thin anodic Al_xO_y film as a gate dielectric layer is prepared using an anodization process. The dual‐channel layer consists of an oxygen‐uncompensated channel layer and an oxygen‐compensated capping layer. It is confirmed that the dual‐channel structure is effective for enhancing device performance and bias stability in comparison with the single‐channel structure. As a result, the dual‐channel ITZO TFT gated with anodic Al_xO_y exhibits an effective saturation mobility of 12.56 cm² Vs⁻¹, a threshold voltage of 0.28 V, a subthreshold swing of 76 mV dec⁻¹, a low‐voltage operation of 1 V, and good operational stability (threshold voltage shift (ΔV_TH) < −0.03 V under a negative gate bias stress and ΔV_TH < 0.15 under positive gate bias stress of 3600 s). The work shows that the ITZO TFTs, based on a dual‐channel layer and an anodic‐oxide gate dielectric layer, have great potential for low‐power, portable, and wearable electronics.