The InAlN/GaN HEMT has been identified as a promising alternative to conventional AlGaN/GaN HEMT due to its enhanced polarization effect contributing to higher 2DEG in the GaN channel. However, the InAlN barrier usually suffers from high leakage and therefore low breakdown voltage. In this paper, we propose an asymmetrical GaN HEMT structure which is composed of an InAlN barrier at the source side and an AlGaN barrier at the drain side. This novel device combines the advantages of high 2DEG density at the source side and low electrical-field crowding at the drain side. According to the TCAD simulation, the proposed asymmetric device exhibits better drain current and transconductance compared to AlGaN/GaN HEMT, and enhanced breakdown voltage compared to InAlN/GaN HEMT. The current collapse effects have also been evaluated from the process-related point of view. Possible higher interface traps related to the two-step epitaxial growth for the asymmetric structure fabrication will not exacerbate the current collapse and reliability.

In this Letter, the impacts of the GaN cap on the gate leakage mechanisms have been investigated in the recessed-gate AlGaN/GaN high-electron-mobility transistors. The recessed gate with GaN cap removal under the gate can be a way to shrink the gate-to-channel distance, therefore improving the current density and the transconductance without sacrificing the interface properties, which play an important role in current collapse. The investigation of gate leakage current, as a reliability issue, on the recessed gate with GaN cap removal is, therefore, important. From the Igs–Vgs measurements at different temperature and stress conditions, it is found that the leakage mechanisms of the recessed-gate devices with cap removal are identical to those of the standard devices. However, the trap energy level is higher when extracted from the two-step trap-assisted tunneling mechanism at high reverse gate bias, resulting in higher leakage current for the recessed-gate device. Besides, stress measurements on the device reveal that the leakage mechanism at low reverse gate bias changes from temperature-independent before stress to temperature-dependent after stress. It is also found that a recoverable trap with a new energy level is generated after stress based on temperature-sensitive characteristics, which corresponds to the Poole–Frenkel emission mechanism.

I-line stepper is widely used in large scale device manufacturing with limited achievable critical dimension by itself. With the aid of the spacer sidewall, the critical dimension can be further shrunk down. Spacer sidewall aided process necessitates an additional deposition-etching process, which inevitably results in process related damage under the gate. This paper proposes an optimized spacer sidewall aided gate patterning procedure for 0.15 μm GaN High Electron Mobility Transistors (HEMTs) fabrication. The process is proved to be effective in improving device performance compared to conventional sidewall process by keeping first Si-rich SiN passivation layer integrity at the gate edge. Interface trap density (Dit) and mobility were extracted for both conventional sidewall process and the optimized one with different passivation layers at the gate edge, demonstrating a lower Dit and higher mobility using the optimized process with enhanced device performances, such as higher current, breakdown voltage, and stress state characteristics, compared to the conventional process, which is promising for mass production of 0.15 μm GaN HEMTs.

This article presents a comprehensive study on the impact of gate recessing strategies on the electrical performances and trap dynamics of 0.15- $\mu $ m aluminum gallium nitride (AlGaN)/gallium nitride (GaN) high-electron-mobility transistors (HEMTs) for high power-added efficiency (PAE) applications. By comparing devices with varying recess depths and their standard nonrecessed counterpart, we systematically investigate the trade-offs between device performance and process-induced damage. Device with GaN cap removal achieves a record output current density of 1393 mA/mm and a peak transconductance of 661 mS/mm, with reduced short-channel effects (SCEs) due to an increase in carrier concentration and a higher ${L}_{\text {g}}$ / ${t}_{\text {AlGaN}}$ . Notably, the gate-recessed device obtains an optimal recess depth with a PAE of 81.6% and Pout of 27.1 dBm at 10 GHz. Through stress measurement and RF transconductance analysis, we quantify the current collapse and the spatial distribution of border traps induced by inductively coupled plasma (ICP) etching. The results highlight that localized GaN cap removal offers a damage-mitigated pathway to enhance gate control, while excessive barrier thinning decreases the 2DEG concentration and exacerbates trap formation, leading to performance degradation. This work provides critical insights into optimizing gate-recessed designs for high-frequency power amplifiers by balancing structural benefits and process-induced defects.

In this article, we experimentally decouple the effects of parasitic capacitance and process-induced current collapse on the RF power-added efficiency (PAE) of $0.25~\mu $ m gallium nitride (GaN)-on-SiC high-electron-mobility transistors (HEMTs) by systematically varying the source-connected field-plate (FP) length. In a standard process with high-surface-trap density, current collapse dominates at 10–18 GHz, and longer FPs yield higher PAE. After process optimization that reduces the interface trap density, the dominant limitation shifts: parasitic output capacitance outweighs collapse, and PAE improves with shorter FPs at both X- and Ku-bands. These results reveal a clear transition from collapse-limited to capacitance-limited efficiency and establish a practical design guideline for FP engineering in millimeter-wave GaN HEMTs.

The efficiency of GaN-on-SiC high-electron-mobility transistors (HEMTs) is limited by the combined influence of the trap-induced current collapse, knee-voltage walkout, and parasitic capacitances. While the gate-length scaling is known to affect these mechanisms, the optimum geometry for maximum power-added efficiency (PAE) under the realistic bias and frequency conditions has remained unclear. Here, we investigate the gate length impacts on efficiency. Comprehensive DC, pulsed-IV, small-signal, and large-signal measurements reveal a nonmonotonic dependence of efficiency, from which a bias-frequency regime map for gate-length optimization has been established, and a predictive model that links PAE to small-signal f_max and applied bias was introduced. The model reproduces measured data with high accuracy and offers a compact route to efficiency prediction from routine RF characterization. Together, the regime map and predictive model provide a physically grounded framework for bias- and frequency-aware design of GaN HEMTs for millimeter-wave power amplification.