The rapid advancement in AI requires efficient accelerators for training on edge devices, which often face challenges related to the high hardware costs of floating-point arithmetic operations. To tackle these problems, efficient floating-point formats inspired by block floating-point (BFP), such as Microsoft Floating Point (MSFP) and FlexBlock (FB), are emerging. However, they have limited dynamic range and precision for the smaller magnitude values within a block due to the shared exponent. This limits the BFP’s ability to train deep neural networks (DNNs) with diverse datasets. This paper introduces the hybrid precision (HPFP) selection algorithms, designed to systematically reduce precision and implement hybrid precision strategies, thereby balancing layer-wise arithmetic operations and data path precision to address the shortcomings of traditional floating-point formats. Reducing the data bit width with HPFP allows more read/write operations from memory per cycle, thereby decreasing off-chip data access and the size of on-chip memories. Unlike traditional reduced precision formats that use BFP for calculating partial sums and accumulating those partial sums in 32-bit Floating Point (FP32), HPFP leads to significant hardware savings by performing all multiply and accumulate operations in reduced floating-point format. For evaluation, two training accelerators for the YOLOv2-Tiny model were developed, employing distinct mixed precision strategies, and their performance was benchmarked against an accelerator utilizing a conventional brain floating point of 16 bits (Bfloat16). The HPFP selection, employing 10 bits for the data path of all layers and for the arithmetic of layers requiring low precision, along with 12 bits for layers requiring higher precision, results in a 49.4% reduction in energy consumption and a 37.5% decrease in memory access. This is achieved with only a marginal mean Average Precision (mAP) degradation of 0.8% when compared to an accelerator based on Bfloat16. This comparison demonstrates that the proposed accelerator based on HPFP can be an efficient approach to designing compact and low-power accelerators without sacrificing accuracy.

The latest convolutional neural network (CNN) models for object detection include complex layered connections to process inference data. Each layer utilizes different types of kernel modes, so the hardware needs to support all kernel modes at an optimized speed. In this paper, we propose a high-speed and optimized CNN accelerator with flexible diagonal cyclic arrays (FDCA) that supports the acceleration of CNN networks with various kernel sizes and significantly reduces the time required for inference processing. The accelerator uses four FDCAs to simultaneously calculate 16 input channels and 8 output channels. Each FDCA features a 4 × 8 systolic array that contains a 3 × 3 processing element (PE) array and is designed to handle the most commonly used kernel sizes. To evaluate the proposed CNN accelerator, we mapped the widely used YOLOv5 CNN model and evaluated the performance of its implementation on the Zynq UltraScale+ MPSoC ZCU102 FPGA. The design consumes 249,357 logic cells, 2304 DSP blocks, and only 567 KB BRAM. In our evaluation, the YOLOv5n model achieves an accuracy of 43.1% (mAP@0.5). A prototype accelerator has been implemented using Samsung’s 14 nm CMOS technology. It achieves 1.075 TOPS, a peak performance with a 400 MHz clock frequency.

This paper presents a 5G new radio (NR) FR2 beamforming system with an integrated transceiver module. A real-time operating module providing enhanced flexibility and capability has been proposed. The integrated RF beamforming system with an integrated transceiver module can be operated in 8Tx-8Rx mode configuration simultaneously. A series-fed structure 8 × 7 microstrip antenna array for compact size and improved directivity is employed in the RF beamforming module. The RF beamforming module incorporates a custom 28 GHz, eight-channel fully differential beamforming IC (BFIC). An eight-channel BFIC in a phased-array beamforming system offers advantages in terms of increased antenna density and improved beam steering precision. The RF beamforming module is integrated with an RF transceiver module that enables the simultaneous up-conversion and down-conversion of the baseband signal. The RF transmitter module consists of a transmitter, a receiver, a signal generator, a power supply, and a control unit. The RF beamforming system can scan horizontally from −50° to +50° with a step of 10°. To achieve an optimized beam pattern, a calibration was conducted. The transmit and receive conversion gain of around 20 dB is achieved with the transceiver module. To verify the communication performance of the manufactured integrated RF beamforming system, a real-time wireless video transmission/reception test was performed at a frequency of 28 GHz, and the video file was transmitted smoothly in real time without interruption within a range of ±50°.

This letter presents a multifunctionality reconfigurable substrate-integrated waveguide (SIW) filter embedded in a microstrip line. The proposed filter used an electromagnetic bandgap structure (EBG) to compact the size and improve the electromagnetic features. The SIW filter consists of a three-cell EBG with metallic circular-shaped connected to the ground through cylindrical vias. Firstly, the base SIW structure offers a wide passband filtering response, and then, to obtain selective passband, wide band rejection, and controllable resonance frequencies, a three-cell EBG along with four diodes has been attached. The filter is designed and printed on a Rogers 4003 substrate with a thickness of 1mm and is experimentally validated for functionalities operated at three modes with an average 3dB bandwidth of 115MHz in each frequency. In addition to that, two transmission zeros (TZ) have been produced in the upper band frequency. The filters response is also tunable by turning the diode off or on and changing the main parameters of EBG, the gab, and the position between cells. The study explores resonance frequency alterations in a three-state system of on/off. By eliminating or diminishing specific modes, and incorporating diodes, distinct resonance behaviors are observed. Moreover, shifting frequency resonance in a multiparameter system has been investigated. Increasing B1 induces a significant shift to lower values, while an increase in D1 leads to a decrease in the first and second resonance frequencies and an upward shift in the third. The designed filter has been fabricated and tested to compare and confirm simulated responses. Simulation and measurement results are in good agreement. The S-parameters of measured results gained a good response (15dB) within the passbands and stopbands and an insertion loss of 1.5dB suitable for 5G and Wi-Fi systems.

한국전자파학회논문지 (The Journal of Korean Institute of Electromagnetic Engineering and Science)

한국전자파학회논문지 (The Journal of Korean Institute of Electromagnetic Engineering and Science)