Zhangsheng Lan

Mr. Zhangsheng Lan

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Research Focus & Metrics

Academic Career Length

3Years (2024-Present)

(Calculated once Scilit publication data is synced: current year − year of first publication + 1)

Representative Publications

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8 March 2024 in Electronics
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Journal Article
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YDYARU DING
YARU DING
ZWZeping Weng
Zeping Weng
ZLZhangsheng Lan
Zhangsheng Lan
CYChu Yan
Chu Yan
DCDaolin Cai
Daolin Cai
YZYi Zhao
Yi Zhao
This work experimentally investigated the wake-up behaviors of hafnium oxide-based ferroelectric capacitors by manipulating the interval time between each characterization cycle. Both Positive-Up–Negative-Down (PUND) and Negative-Down–Positive-Up (NDPU) waveforms were used as the stress and measurement waveforms in the experiments. It was found that the imprint occurs as the total interval time increases to a several-seconds level. However, this only affects the remnant polarization (PR) of ferroelectric capacitors when stressed by NDPU waveforms, since the voltage amplitude saturates under the PUND stress conditions and does not influence the PR. The wake-up behavior has been proved to be caused by the defects redistribution during electrical cycling. Notably, when using PUND waveforms, the change in the interval time can result in different increase rates of PR, indicating the possibility of recovery during the intervals. This recovery leads to a slower wake-up when cycling with a longer interval time. Moreover, it is observed that this PR recovery could reach saturation after several seconds of the interval time. This comprehensive investigation of wake-up and imprint behaviors can provide new insights to evaluate and enhance the reliability of ferroelectric memories.

27 March 2024 in Journal of Applied Physics
Verified
Journal Article
Open access
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ZCZhengyang Chen
Zhengyang Chen
ZLZhangsheng Lan
Zhangsheng Lan
YLYiran Lin
Yiran Lin
NTNishimura Tomonori
Nishimura Tomonori
CLChoongHyun Lee
ChoongHyun Lee
YZYi Zhao
Yi Zhao
This paper presents a comprehensive exploration of low interface trap density (Dit) in HfO2/Si0.73Ge0.27 metal-oxide semiconductor (MOS) capacitors achieved through sulfur passivation and post-deposition annealing (PDA). Our investigation revealed that devices subjected to sulfur passivation and PDA exhibit noteworthy reductions in Dit and hysteresis. Specifically, a low Dit value of 1.2 × 1011 eV−1 cm−2 has been achieved at Ei–0.1 eV for the SiGe MOS device. The observed enhancement in interface properties can be attributed to two key factors: the reduction of the GeOx concentration in the interfacial layer (IL) by sulfur passivation on the SiGe surface and the IL densification with stoichiometric oxygen during PDA.