In this study, the channel length dependence of hot carrier degradation (HCD) in ultra-scaled nFinFETs is experimentally investigated with the self-heating correction. By electrical characterizations of nFinFETs with different channel lengths, the novel insight into the HCD mechanism is proposed upon considering the trap behaviors, including both interface traps and oxide traps. Our experimental results show that the proportion of interface traps in total traps is strongly dependent on the channel length. Furthermore, the interface traps induced by HCD are located near the source side in ultra-scaled nFinFETs, which is different from the phenomena in long channel devices.

This work experimentally investigated the wake-up behaviors of hafnium oxide-based ferroelectric capacitors by manipulating the interval time between each characterization cycle. Both Positive-Up–Negative-Down (PUND) and Negative-Down–Positive-Up (NDPU) waveforms were used as the stress and measurement waveforms in the experiments. It was found that the imprint occurs as the total interval time increases to a several-seconds level. However, this only affects the remnant polarization (P_R) of ferroelectric capacitors when stressed by NDPU waveforms, since the voltage amplitude saturates under the PUND stress conditions and does not influence the P_R. The wake-up behavior has been proved to be caused by the defects redistribution during electrical cycling. Notably, when using PUND waveforms, the change in the interval time can result in different increase rates of P_R, indicating the possibility of recovery during the intervals. This recovery leads to a slower wake-up when cycling with a longer interval time. Moreover, it is observed that this P_R recovery could reach saturation after several seconds of the interval time. This comprehensive investigation of wake-up and imprint behaviors can provide new insights to evaluate and enhance the reliability of ferroelectric memories.

In this work, we explore the material potential of yttrium-content GeO _x (YGO) in the design of a charge-trapping gate stack for embedded non-volatile memory (eNVM), which can share common gate stack materials with Ge logic CMOS. Based on a deep understanding of YGO, we propose a Ge eNVM with an oxidation-induced self-assembled YGO layer as the charge trapping layer. An eNVM fabricated on Ge offers a fast program/erase (P/E) speed (50 $\mu \text{s}$ and 2 ms for program and erase operations, respectively), low-voltage operation, a data retention lifetime of >10 years, and an endurance of > 10 ⁵ P/E cycles.

In this work, we investigate the self-rectifying behaviors of the resistive random access memory (RRAM) fabricated on n-Ge substrates, featuring an ultrahigh rectifying ratio ( $>$ 10 $^{\text{5}}$ ), a high ON/OFF ratio ( $>$ 500), and low operation voltages. The excellent performances of the Ge-based RRAM in this study are attributed to the Fermi-level pinning (FLP) near the valence band edge of n-Ge through the localized conductive filaments in HfO $_{\text{2}}$ . In addition, the underlying mechanism of the FLP behaviors in RRAM on n-Ge substrates is discussed. The electrical properties of the self-rectifying RRAM, including superior data retention, excellent uniformity, decent switching speed, endurance, and robust read/write disturbance immunity, are characterized comprehensively. The FLP-induced superior rectifying behaviors and excellent electrical properties of the RRAM enable the potential application of the high-density nonvolatile memory.

In this study, we propose a new matrix version of the existing dielectric breakdown (BD) percolation model for non-uniform defect generation. Its calculation framework is established utilizing the graph theory of discrete mathematical. This new model is verified by applying to the case of high-k/interfacial layer bilayer gate stack. Furthermore, we also demonstrate the potential of this model in its application to MOSFET’s off-state TDDB or other complex situations by incorporating the TCAD simulations. The flexibility and extensibility of the model is beneficial for further understanding the physical mechanisms of dielectric breakdown in general cases.

As semiconductor devices approach the sub-10 nm technology node, the self-heating effect (SHE) induced by confined geometries (e.g., FinFETs and nanosheet FETs) has emerged as a critical bottleneck affecting both performance and reliability. This challenge has prompted extensive research efforts to develop advanced characterization methodologies to investigate this effect and its corresponding influence on the device’s reliability issues. In this paper, we propose reflection-based ultra-fast measurement techniques for the continuous monitoring of the self-heating effect in advanced MOSFETs. With this approach, the self-heating effect-induced degradation of transistor drain current and the real-time temperature change can be continuously captured using a digital phosphor oscilloscope on a nanosecond scale. The thermal time constant of 17 ns and the thermal resistance of 34,000 K/W have been extracted for the short channel transistors used in this study with the help of this new characterization method. This reflection-based method is useful for the fast extraction of the thermal time constant and thermal resistance and for the continuous monitoring of current degradation as well as the real-time temperature. Therefore, this new characterization method is beneficial for the evaluation of the self-heating effect in advanced ultra-scaled MOSFETs.