This paper introduces a high-speed mixed-signal readout array in 130-nm CMOS for the amplification and digitization of picoampere-range signals. Its design is inspired by the needs of emerging DNA sequencing technologies based on biological nanopore sensors. To overcome switching and substrate noise this system adopts an in-pixel analog-to-digital converter (ADC) architecture and a novel readout technique while consuming 10x less power than similar designs described in the literature. The in-pixel ADC architecture is inherently scalable and immune to electrical interference which can be extended to 100s of channels. With a 5 pF input capacitance, the amplifiers achieve a maximum bandwidth of 100 kHz and demonstrate a noise floor as low as 4 fA/ $\sqrt {\text{Hz}}$ and a gain in the range of $\text{G}\Omega $ at 10 kHz. Circuit noise behaviour and theoretical maximum performance estimates using behavioural models are also discussed.

Power usage reduction and efficiency enhancement of measurement devices are a major challenge in self-powered wireless sensor nodes and also sensors implanted in the human body. Such instruments should be usually operated using the limited environmental energy resources. Electrochemical sensors and potentiostats are extensively used in this context for the measurement of chemical components. In these cases, a lot of research has focused on internal processing blocks power reduction of the potentiostat circuit. In this paper, a discrete current mode (DCM) switching potentiostat is presented, which can significantly reduce the static power usage at the output stage of the potentiostat compared with linear output stage counterparts. Using time-domain analyses, the unexpected oscillatory behavior of a continuous current mode (CCM) output stage switching potentiostat is investigated. Consecutively, it is shown that in current fabrication processes, this configuration will consume more power than the DCM topology. The correctness of the designs and analyses are shown using both simulation and experimental results. The simulated 0.18-μm CMOS DCM output stage potentiostat has an efficiency of 95% at an output load of 12 μA, while the long-channel MOSFET-based prototype implementation shows an efficiency of 64%.

The input capacitance of the SAR ADC is considered as a drawback in many applications. In this paper, a 12-bit low-power SAR ADC with low-input capacitance SAR based on separated DAC and sample-and-hold blocks (SB) structure is proposed. The SB structure suffers from variation of the input common-mode voltage of the comparator causing nonlinear input-referred offset and kickback noise. Here, a closed loop low-power rail-to-rail offset cancellation technique for the comparator based on the body voltage tuning is proposed. In order to stabilize the closed loop structure, the open loop gain is controlled by adapting the gain of the preamplifier. Using this structure, the rail-to-rail offset is kept lower than 110 μV and the overall power of the comparator is 1 pJ/Conv. Complementary-clocked dynamic branches are exploited at the input the comparator to decrease the common-mode dependent kickback noise error to less than 1 LSB. The bootstrapped switch’s controlling signal is also modified to achieve less than 1 LSB error and 18.9% less power consumption. The proposed ADC is designed in standard 180 nm CMOS technology with a 1.8 V supply voltage and shrinking the input capacitance to 2 pF, which leads to 41 nW power consumption in the input voltage supply. Electrical simulations including PVT, Monte-Carlo, and post-layout parasitic extraction were run to ensure the effectiveness of the approach. The ADC features an ENOB of 11.1-bit and the sampling rate of 1 MHz with a power consumption of 117.9 μW including the input power supply which are competitive with the state-of-the-art, and demonstrate the virtue of the proposed approach.

Low power wireless standalone sensors which can operate without any wiring have received significant attention in sensor network applications. These devices harvest environmental energy resources to supply their power and transfer their collected data using wireless RF links. In many instances the power supplied from the environment is far less than the power required by the sensor device. In this case the main solution is to accumulate energy on a storage element and when enough energy is stored, the sensor node is instantaneously activated using an under voltage lockout, UVLO, circuit. During this short time burst, the sensor performs the required acquisition, transmits the results and enters a sleep mode until again enough energy is collected. The quiescent current of the UVLO is the main factor that determines the minimum power level at which the sensor node is still operational. Most wake-up circuits used in conventional devices suffer from a quiescent current of a few hundred nanoamperes. In this work, using a zero bias current MOSFET based approach, a new wake-up circuitry is presented which lowers the quiescent current down to the picoampere range. As a practical application, the effectiveness of the proposed circuit is shown in a soil moisture monitoring sensor setup.