In this article, we address the problem of synchronizing multiple analog-to-digital converter (ADC) and digital-to-analog converter (DAC) chains in a multi-channel system, which is constrained by the sampling frequency and inconsistencies among the components during system integration. To evaluate and compensate for the synchronization differences, we propose a pulse compression shape-based algorithm to measure the entire delay parameter of the ADC/DAC chain, which achieves sub-sampling resolution by mapping the shape of the discrete pulse compression peak to the signal propagation delay. Moreover, owing to the matched filtering in the pulse compression process, the algorithm exhibits good noise performance and is suitable for wireless scenarios. Experiments verified that the algorithm can achieve precise measurements with sub-sampling resolution in scenarios where the signal-to-noise ratio (SNR) is greater than −10 dB.

With the increase of the rated voltage and current of the high-voltage self-energy SF 6 circuit breaker, its breaking performance design is facing an astonishing challenge. The breaking performance of the circuit breaker is related to the generation, development and dissipation of high temperature airflow during the arc process. The gas flow causes the temperature of the expansion chamber is generally too high, resulting in the temperature of the arc cooling environment is too high at the current zero time. In some cases, it will lead to short-circuit current breaking failure. For the high-voltage self-energy SF6 circuit breaker, by simulating the entire arc breaking process, the expansion chamber gas pressure and temperature in the high current stage were obtained. At the same time, the arc shape and arc extinguishing environmental parameters in the current zero stage were obtained. Based on the results of arc simulation, the design of the expansion chamber structure was optimized, and simulation verification was performed again. Simulation results show that after the optimized design of the expansion chamber structure, the overall temperature of the arc-extinguishing environment at the current zero time decreases. The validity of this method is verified by comparison with the breaking test of the original circuit breaker prototype. The results show that the optimization design of the expansion chamber structure based on the arc simulation results can quickly and accurately determine the shape and size of the arc extinguishing chamber and significantly improve the breaking performance of the breaker.

Mechanical failures is most in all failures of circuit breaker. The mechanical reliability of circuit breaker is very crucial for power grid safety. In order to improve the mechanical reliability of circuit breaker, at the same time, in order to reduce costs and improve the competitiveness of products in the market, the mechanical reliability of circuit breaker needs to be studied. The dynamic behavior of circuit breaker is studied by computer simulation. Firstly, the circuit breaker is meshed by HyperMesh, then Ls-dyna is used to calculate the transmission of the circuit breaker. After the calculation is completed, the results are checked by experiment. Optimize the circuit breaker structure according to the result.

This brief presents a pipelined floating-point Multiply–Accumulator (FPMAC) architecture designed to accelerate sparse linear algebra operations. By designing a lookup-table-based 5–3 carry-save adder (CSA) and combining it with a 3–2 CSA, the proposed design minimizes the critical path and boosts operational speed. Moreover, the proposed architecture takes advantage of data characteristics in sparse linear algebra to displace the shift unit in the critical accumulation loop, further increasing the throughput rate. In addition, the integration of a lookup-table-based leading-zero anticipator (LZA) enhances normalization efficiency. Experimental results show that, compared with reported FPMAC designs, the proposed architecture may achieve a significantly higher maximum clock frequency for single-precision floating-point operations.

On the basis of ensuring insulation and current carrying capacity, set the electric field and temperature as constraints, the GIS/GIL co-simulation model was established with the least cost as the optimization goal. The optimization process usually requires hundreds of iterative calculations, which resulted in inefficiency of the complex and time-consuming 2D/3D co-simulation model and difficulties of meeting the needs of product development. Firstly, cosimulation models of static electric field, eddy current and dynamic fluid were established. Then using the Latin hypercube sampling method, 50 samples were extracted from the optimized sample space, and the sensitivity analysis was performed based on the results of co-simulation model. Based on the sensitivity analysis results, the simplified model was established by using the least squares fitting method. The simplified model results are verified by co-simulation model. The results showed that calculation consistency of simplified model with co-simulation model is about 98.9%, while the computational efficiency of the simplified model is 4000 times that of the co-simulation model. After optimization, the busbar cost is reduced by 26.65% on the basis of ensuring insulation and current-carrying performance.