This paper presents a low-latency coordinate rotation digital computer (CORDIC) algorithm to accelerate the computation of arctangent functions, and it describes the corresponding iterative and pipelined architecture of this novel algorithm. As compared to the existing methods based on CORDIC, the proposed method can effectively reduce the number of iterations by dedicated pre-rotation and comparison processes. Moreover, the proposed CORDIC algorithm supports all vectors with arbitrary angles while maintaining convergence. By error analysis, the proposed algorithm can achieve the same accuracy as the conventional CORDIC algorithm during floating-point arctangent function computation and reduce the number of iterations by approximately 50%. This paper presents two new architectures—the iterative architecture, which can be more resource efficient, and the pipelined architecture, which can achieve a throughput rate of one datum per clock. Finally, the experimental comparison results indicate that the proposed method outperforms extant methods as it exhibits low latency, requires fewer resources to compute the arctangent function for floating-point inputs, and necessitates no digital signal processing (DSP) and memory for fixed-point inputs.

In this brief, we present a novel pipelined architecture for real-valued fast Fourier transform (RFFT), which is dedicated to processing serial input data. An optimized algorithm is proposed for stage division in RFFT to achieve an area-efficient RFFT computing structure with full hardware utilization. A single path butterfly and a real rotator are merged into one processing element (PE) in each stage, except the last stage, to reduce hardware resource utilization. In addition, a novel shift-adder is designed for $N$ -point RFFT with $W$ -bit signals, and a new data management method based on the PEs is proposed, which saves resources with a more regular flow graph.

This brief introduces an optimised architecture for a serial commutator (SC) pipelined fast Fourier transform (FFT) with fully real data paths, utilising a novel data management scheme based on bit-dimension permutation circuits. By employing this approach, we minimised multiplexer utilisation by 80% in every processing element (PE) and 50% in every permutation circuit of each stage compared to the conventional SC architecture. Additionally, the proposed structure achieved full hardware utilisation with a natural-order input/output (I/O) datastream. Experimental results demonstrate that our architecture reduced look-up table (LUT) logic by 31% compared to the prior design.

In this article, we address the problem of synchronizing multiple analog-to-digital converter (ADC) and digital-to-analog converter (DAC) chains in a multi-channel system, which is constrained by the sampling frequency and inconsistencies among the components during system integration. To evaluate and compensate for the synchronization differences, we propose a pulse compression shape-based algorithm to measure the entire delay parameter of the ADC/DAC chain, which achieves sub-sampling resolution by mapping the shape of the discrete pulse compression peak to the signal propagation delay. Moreover, owing to the matched filtering in the pulse compression process, the algorithm exhibits good noise performance and is suitable for wireless scenarios. Experiments verified that the algorithm can achieve precise measurements with sub-sampling resolution in scenarios where the signal-to-noise ratio (SNR) is greater than −10 dB.

This brief presents a novel pipeline architecture designed to compute the fast Fourier transform (FFT) on real input signals in a serial format. This architecture significantly improves resource efficiency by sharing adders between butterfly and rotator structures. In addition, a novel data management approach for N-point radix-2 serial real-valued FFT (RFFT) has been proposed, which not only simplifies the data reordering circuit between processing elements (PEs) but also achieves natural order data output. The real-valued 1024-point FFT has been implemented on a field-programmable gate array (FPGA). Compared with typical real-valued serial commutator (RSC) FFT architecture, the proposed architecture achieves substantial improvement, including a reduction of 10.3% in the number of lookup tables (LUTs) and 12.5% in flip-flops (FFs).

This brief introduces an optimized architecture for serial commutator (SC) pipelined fast Fourier transform (FFT) with fully-real data paths, utilizing a novel data management scheme based on bit-dimension permutation circuits. By employing this approach, we minimized multiplexer utilization by 80% in every processing element (PE) and 50% in every permutation circuit of each stage compared to the conventional SC architecture. Additionally, the proposed structure achieved full hardware utilization with a natural order input/output (I/O) datastream. Experimental results demonstrate that our architecture reduced look-up table (LUT) logic by 31% compared to the prior design.