We report recent advances in photonic–electronic integration developed in the European research project L3MATRIX. The aim of the project was to demonstrate the basic building blocks of a co-packaged optical system. Two-dimensional silicon photonics arrays with 64 modulators were fabricated. Novel modulation schemes based on slow light modulation were developed to assist in achieving an efficient performance of the module. Integration of DFB laser sources within each cell in the matrix was demonstrated as well using wafer bonding between the InP and SOI wafers. Improved semiconductor quantum dot MBE growth, characterization and gain stack designs were developed. Packaging of these 2D photonic arrays in a chiplet configuration was demonstrated using a vertical integration approach in which the optical interconnect matrix was flip-chip assembled on top of a CMOS mimic chip with 2D vertical fiber coupling. The optical chiplet was further assembled on a substrate to facilitate integration with the multi-chip module of the co-packaged system with a switch surrounded by several such optical chiplets. We summarize the features of the L3MATRIX co-package technology platform and its holistic toolbox of technologies to address the next generation of computing challenges.

Novel Data Center (DC) architectures based on resource disaggregation, hold the potential to increase resource utilization at a reduced energy and cost envelope, imposing however significant challenges in the underlying DC network infrastructure, that has to provide high-radix and high bandwidth connectivity, while maintaining sub-μs latency. At the same time, the explosive growth of AI applications, has transformed the traffic profiles on the majority of DC workloads, calling for support of advanced network functionalities, such as multicasting. In this direction, we scale-up the Hipoλaos Optical Packet Switch (OPS) architecture to a thousand-port layout, at the same time upgrading its functionality to allow latency-free intra-tray multicasting. The feasibility of a 10.24 Tb/s capacity switch fabric with a 10 Gb/s line-rate in a 1024-port configuration, with 4-packet buffering capacity is experimentally demonstrated, revealing error-free performance with <3.4dB power penalty. Optical multicasting to up-to 5 nodes is also experimentally validated at 10 Gb/s, with a power penalty variation of less than 1dB between the different output ports, while multicast operation across the whole required spectral range of a 1024-port switch is investigated, utilizing pairs of wavelengths with different channel spacing. Network-level analysis of the 1024-port Hipoλaos switch, revealed sub-μsec p90-latency and ~85% throughput, for the unicast case, when utilizing a 2-packet-buffer design. Finally, the simulation model was extended to support the Hipoλaos multicast friendly layout, revealing up to 4250% throughput improvement, as compared to the conventional layout, while maintaining sub-μs latency.

We demonstrate experimental evidence of the data capture and the low-energy thermo-optic tuning credentials of dielectric-loaded plasmonic structures integrated on a silicon chip. We show 7-nm thermo-optical tuning of a plasmonic racetrack-resonator with less than 3.3 mW required electrical power and verify error-free 10-Gb/s transmission through a 60-μm-long dielectric-loaded plasmonic waveguide.

We demonstrate experimentally an optical switch architecture that employs μm-silicon-on-insulator (SOI)-based circuitry for both buffering and routing purposes and operates with 10-Gb/s optical packets in both uniand multi-cast switching forwarding modes. It comprises a hybrid broadcast-and-select (BS)/wavelength-routed architecture, with the BS layout being responsible for identifying the desired cluster of outgoing ports, while the wavelength-routed switch part forwards then the data to the specific outgoing port. Contention resolution at the BS switch part is offered through an μm-SOI integrated optical delay line bank and wavelength-routing is realized by means of a μm-SOI 3 × 3 echelle grating router, while semiconductor optical amplifier Mach-Zehnder interferometers are employed for wavelength conversion purposes. The switch architecture has been experimentally validated with 10-Gb/s optical data packets for both uniand multicasting operation, revealing error-free performance with c5-dB power penalty.

We discuss the challenges and limitations of current electrical DataCenter switches towards scaling beyond the 25.6Tb/s capacity-era while meeting a low-latency and high-radix envelope. With the high-power SerDes and required DSP interfaces forming critical scaling factors, we discuss the perspectives and challenges of migrating to Optical Packet Switch (OPS) technologies for avoiding the electronically-induced bottlenecks, while exploiting reliable and practical techniques for overcoming well-known OPS problems, like buffering and high-port connectivity. We demonstrate the feasibility of OPS schemes by reporting experimental results of our Hipoλaos architecture towards extending its line-rate to 25Gb/s per port and enabling 25.6Tb/s switch capacities through a 1024-radix layout, while still preserving sub-usec latency metrics. Experimental results are presented for both unicast and multicast packets, employing the 1024-radix Hipoλaos architecture in a fully-fledged FPGA-controlled switching Plane, along with a 32x32 Arrayed Waveguide Grating Router (AWGR) device. The unicast performance is validated through BER measurements, while optical multicasting to 5 nodes is also experimentally evaluated at 25Gb/s, along with an evaluation of the broadband multicast capabilities of the switch. Moreover, a mixed-traffic scenario involving both unicast and multicast traffic is demonstrated. Finally, a discussion about the perspectives and challenges of bringing OPS in DC networks is presented.

We demonstrate an on-chip 0.96 TOPS hyperdimensional photonic tensor core by utilizing a time-space-wavelength multiplexed silicon photonic Crossbar (Xbar). The novel architecture relies on serializing the large matrix-vector or tensor-vector products by unfolding multiply and accumulation operations over the time domain, while simultaneously distributing the computational workload over different spatial and wavelength channels. We experimentally demonstrate the operation of a 4-channel 2-input time-space-wavelength division multiplexing (TSWDM) Xbar that incorporates 56 GHz electro-absorption modulators (EAMs) and 4-channel integrated multiplexing stages. Its successful operation as a 4×2×1 tensor-vector multiplication unit demonstrated an average relative error of 3.9%. Its performance as a photonic AI accelerator was also evaluated in the classification task of the Iris dataset, presenting experimental accuracies of 93.3% at data rates between 4×10 and 4×30 GBd, reaching 83.3% when the data rate increases to 4×60 GBd. Finally, we discuss the TSWDM Xbar scalability potential, revealing that the inclusion of a wavelength division multiplexing (WDM) scheme in the space division multiplexing (SDM) architecture reduces the operating laser power, feasibly boosting the potential of constructing photonic accelerators with computational throughput in the POPS regime.