Jian Ji

Dr. Jian Ji


Research Focus & Metrics

Academic Career Length

3Years (2024-Present)

(Calculated once Scilit publication data is synced: current year − year of first publication + 1)

Representative Publications

View All Publications
2 May 2025 in Micromachines
Verified
Journal Article
Open access
PDF file
LZLili Zhai
Lili Zhai
Xiangdong LiXiangdong Li
Xiangdong Li
JJJian Ji
Jian Ji
LYLu Yu
Lu Yu
LCLiang Chen
Liang Chen
JZJincheng Zhang
Jincheng Zhang
The explosive demand for high-performance secondary power sources in artificial intelligence (AI) has brought significant opportunities for low-voltage GaN devices. This paper focuses on research on high-efficiency and high-reliability low-voltage p-GaN gate HEMTs with a gate–drain distance, LGD, of 1 to 3 μm in our pilot line, manufactured on 6-inch Si using a CMOS-compatible process, with extraordinary wafer-level uniformity. Specifically, these fabricated p-GaN gate HEMTs with an LGD of 1.5 μm demonstrate a blocking voltage of over 180 V and a high VTH of 1.6 V and exhibit a low RON of 2.8 Ω·mm. It is found that device structure optimization can significantly enhance device reliability. That is, through the dedicated optimization of source field plate structure and interlayer dielectric (ILD) thickness, the dynamic ON-resistance, RON, degradation of devices with an LGD of 1.5 µm was successfully suppressed from 60% to 20%, and the VTH shift was significantly reduced from 1.1 to 0.5 V. Further, the devices also passed preliminary gate bias stress and high-voltage OFF-state stress tests, providing guidance for preparing high-performance, low-voltage p-GaN gate HEMTs in the future.

2 August 2024 in Micromachines
Verified
Journal Article
Open access
PDF file
ZJZhang Jie
Zhang Jie
Xiangdong LiXiangdong Li
Xiangdong Li
JJJian Ji
Jian Ji
SYShuzhen You
Shuzhen You
LCLong Chen
Long Chen
JZJincheng Zhang
Jincheng Zhang
The application of GaN HEMTs on silicon substrates in high-voltage environments is significantly limited due to their complex buffer layer structure and the difficulty in controlling wafer warpage. In this work, we successfully fabricated GaN power HEMTs on 6-inch sapphire substrates using a CMOS-compatible process. A 1.5 µm thin GaN buffer layer with excellent uniformity and a 20 nm in situ SiN gate dielectric ensured uniformly distributed VTH and RON across the entire 6-inch wafer. The fabricated devices with an LGD of 30 µm and WG of 36 mm exhibited an RON of 18.06 Ω·mm and an off-state breakdown voltage of over 3 kV. The electrical mapping visualizes the high uniformity of RON and VTH distributed across the whole 6-inch wafer, which is of great significance in promoting the applications of GaN power HEMTs for medium-voltage power electronics in the future.