In this work, fast sweeping characterization with an extremely short relaxation time was used to probe the VTH instability of p-GaN gate HEMTs. As the ID-VG sweeping time deceases from 5 ms to 5 μs, the VTH dramatically degenerates from 3.13 V to 1.76 V, meanwhile the hysteresis deteriorates from 22.6 mV to 1.37 V. Positive bias temperature instability (PBTI) measurement by fast sweeping shows the VTH features a very fast shifting process but a slower recovering process. D-mode HEMTs counterpart without Mg contamination demonstrates a negligible VTH shift and hysteresis, proving the VTH instability is probably due to the ionization of acceptor-like traps in the p-GaN depletion region. Finally, the VTH instability is verified by a GaN circuit under switching stress. The VTH instability under different sweeping speed uncovers the fact that the high VTH by conventionally slow DC measurements is probably artificial. The DC VTH should be high enough to avoid HEMT faulty turn-on.

Co-integration of the key power stage, namely gate drivers and half-bridge in a single-die solution, is a tremendous and inevitable challenge to realizing GaN power integrated circuits (GaN power ICs). In this letter, a monolithically integrated GaN half-bridge including the drivers were successfully fabricated on 200-mm engineered substrates of Qromis substrate technology (QST ^® ). Deep trench isolation together with the buried oxide of the GaN-on-QST ^® isolates the high side, low side, and the drivers. While on GaN-on-Si, the back-gating effect more and more impedes the integration of a half-bridge’s low side and high side as the voltage increases. This effect is fully eliminated using the proposed effective isolation strategy. In this letter, we will present a single-die GaN power IC exhibiting 200-V swift switching capability. Finally, based on this GaN power IC, a 48V-to-1V single-stage buck converter was successfully demonstrated.

The backgating effect on trench-isolated enhancement-mode p-GaN devices fabricated on 200-mm GaN-on-SOI was investigated. We show that to minimize the backgating effect in the monolithically integrated half-bridge, the sources of both the low side and high side need to be connected to their respective fully isolated Si(111) device layers to keep the substrates and the sources at equipotential.

To get a better insight into the vertical leakage mechanism of GaN-on-Si, the carrier transport from n⁺, n, p⁺, and p-Si(111) substrates through the AlN nucleation layer was investigated. A plateau in the current-voltage curve was found only for the AlN/p-Si heterojunction due to depletion of the p-Si substrate. Detailed study illustrated that it was the leaky AlN that cannot effectively block the increasing amount of electrons in the inversion layer at the interface and triggered the depletion. Temperature-dependent characterization suggested that the forward vertical leakage mechanism of AlN/Si could be explained sequentially by Ohm's law, space-charge-limited conduction, variable-range hopping, and trap-assisted tunneling. A model involving shallow donor traps, interface traps, and deep level traps was proposed to explain the leakage characteristics. This paper shows that the carrier concentration of the Si substrates strongly impacts the vertical leakage characteristics, and also that the carrier transport from the Si substrate through the AlN nucleation layer is heavily influenced by traps.

In this letter, the dynamic R _on degradation mechanisms of the p-GaN gate HEMTs induced by off-state stress are investigated with different passivation dielectrics AlON and SiN. The degradation mechanisms are twofold, including V _TH shift and surface trapping in the gate-to-drain access region, whose impacts are successfully distinguished. Surface trapping by SiN passivation is evidently proved to be the dominant factor that can almost induce a full current collapse. The V _TH positive shift diminishes the drain current by shrinking the overdrive V _GS , which however, can be compensated by a higher V _GS overdrive in applications. SiN passivation can effectively suppress the positive bias temperature instability effect, probably by passivating the p-GaN fast traps with hydrogen during passivation. Last, the transient measurements unveil that both the surface trapping and V _TH shift have a very slow recovery process.

In this paper, we have extensively investigated the impact of anode recess on the reverse leakage current, forward voltage ( ${V}_{F}$ ), and dynamic characteristics of Au-free AlGaN/GaN Schottky barrier diodes with a gated edge termination (GET-SBDs) on 200-mm silicon substrates. By increasing the number of atomic layer etching (ALE) cycles for anode recessing, we have found that: 1) the reverse leakage current is strongly suppressed due to a better electrostatic control for pinching off the channel in the GET region; a median leakage current of $\sim 1$ nA/mm and an ${I}_{\mathrm{\scriptscriptstyle ON}}/{I}_{\mathrm{\scriptscriptstyle OFF}}$ ratio higher than $10^{8}$ have been achieved in GET-SBDs with six ALE cycles; 2) the forward voltage ( $\sim 1.3$ V) is almost independent of the ALE cycles, taking into account its statistical distribution across the wafers; 3) when the remaining AlGaN barrier starts to be very thin (in the case of six ALE cycles), a spread of the ON-resistance, mainly attributed to the GET region, can occur due to the difficult control of the remaining AlGaN thickness and surface quality; and 4) the dynamic forward voltage of GET-SBDs shows a mild dependence on the ALE process in pulsed $I$ – $V$ characterization, and a more ALE-dependent dynamic ON-resistance is observed.