Monolithic integration of a half bridge on the same GaN-on-Si wafer is very challenging because the devices share a common conductive Si substrate. In this letter, we propose to use GaN-on-SOI (silicon-on-insulator) to isolate the devices by trench etching through the GaN/Si(111) layers and stopping in the SiO ₂ buried layer. By well-controlled epitaxy and device fabrication, high-performance 200 V enhancement-mode (e-mode) p-GaN high electron mobility transistors with a gate width of 36 mm are achieved. This letter demonstrates that by using GaN-on-SOI in combination with trench isolation, it is very promising to monolithically integrate GaN power systems on the same wafer to reduce the parasitic inductance and die size.

In this work, fast sweeping characterization with an extremely short relaxation time was used to probe the VTH instability of p-GaN gate HEMTs. As the ID-VG sweeping time deceases from 5 ms to 5 μs, the VTH dramatically degenerates from 3.13 V to 1.76 V, meanwhile the hysteresis deteriorates from 22.6 mV to 1.37 V. Positive bias temperature instability (PBTI) measurement by fast sweeping shows the VTH features a very fast shifting process but a slower recovering process. D-mode HEMTs counterpart without Mg contamination demonstrates a negligible VTH shift and hysteresis, proving the VTH instability is probably due to the ionization of acceptor-like traps in the p-GaN depletion region. Finally, the VTH instability is verified by a GaN circuit under switching stress. The VTH instability under different sweeping speed uncovers the fact that the high VTH by conventionally slow DC measurements is probably artificial. The DC VTH should be high enough to avoid HEMT faulty turn-on.

Co-integration of the key power stage, namely gate drivers and half-bridge in a single-die solution, is a tremendous and inevitable challenge to realizing GaN power integrated circuits (GaN power ICs). In this letter, a monolithically integrated GaN half-bridge including the drivers were successfully fabricated on 200-mm engineered substrates of Qromis substrate technology (QST ^® ). Deep trench isolation together with the buried oxide of the GaN-on-QST ^® isolates the high side, low side, and the drivers. While on GaN-on-Si, the back-gating effect more and more impedes the integration of a half-bridge’s low side and high side as the voltage increases. This effect is fully eliminated using the proposed effective isolation strategy. In this letter, we will present a single-die GaN power IC exhibiting 200-V swift switching capability. Finally, based on this GaN power IC, a 48V-to-1V single-stage buck converter was successfully demonstrated.

The backgating effect on trench-isolated enhancement-mode p-GaN devices fabricated on 200-mm GaN-on-SOI was investigated. We show that to minimize the backgating effect in the monolithically integrated half-bridge, the sources of both the low side and high side need to be connected to their respective fully isolated Si(111) device layers to keep the substrates and the sources at equipotential.

In this work, GaN HEMTs on 6-inch sapphire substrates are successfully demonstrated for potential 1700 V power applications. The 1.5 μm GaN buffer features a well-controlled crystal quality and uniformity. Benefiting from the insulating sapphire substrate, the buffer vertical leakage channel is cut off, and the lateral parasitic channel at the epitaxy/substrate interface is also significantly suppressed. The fabricated d-mode HEMTs with L _GD of 30 μm highlight a high blocking voltage over 3000 V and a low ON-resistance of 17 Ω·mm. The thin-buffer GaN-on-sapphire technology can significantly reduce the epitaxy and processing difficulties, reduce cost, and enable GaN as a strong competitor for 1700 V and even higher-level power applications.

This paper presents an extensive investigation of the impact of the resistivity of the silicon substrate on the vertical leakage and charge trapping in 200 V GaN-on-Si enhancement-mode high-electron mobility transistors. Three wafers having different substrate resistivities were submitted to combined DC characterization, step-stress experiments, and electroluminescence (EL) analysis. The results described within this paper demonstrate that: 1) the use of a highly resistive silicon substrate can increase the vertical breakdown voltage of the transistors, due to the fact that the voltage drop on the GaN buffer is mitigated by the partial depletion of the substrate (this latter causes a plateau region in the drain to substrate I-V characteristic) and 2) highly resistive substrate results in stronger trapping effects, due to the capacitance of the depleted substrate and the resulting backgating effects. The results described within this paper indicate that the choice of the resistivity of the substrate is the result of a tradeoff between high breakdown voltage (that could be in principle achieved through a highly resistive substrate) and the minimization of trapping processes (which can be hardly obtained with a resistive substrate).