In digitally controlled dc-dc converters with a single voltage feedback loop, the two quantizers, namely the analog-to-digital (A/D) converter and the digital pulse-width modulator (DPWM), can cause undesirable limit-cycle oscillations. In this paper, static and dynamic models that include the quantization effects are derived and used to explain the origins of limit-cycle oscillations. In the static model, existence of dc solution, which is a necessary no-limit-cycle condition, is examined using a graphical method. Based on the generalized describing function method, the amplitude and offset-dependent gain model of a quantizer is applied to derive the dynamic system model. From the static and dynamic models, no-limit-cycle conditions associated with A/D, DPWM and compensator design criteria are derived. The conclusions are illustrated by simulation and experimental examples

Metasurfaces, the two-dimensional counterpart of metamaterials, have caught great attention thanks to their powerful capabilities on manipulation of electromagnetic waves. Recent times have seen the emergence of a variety of metasurfaces exhibiting not only countless functionalities, but also a reconfigurable response. Additionally, digital or coding metasurfaces have revolutionized the field by describing the device as a matrix of discrete building block states, thus drawing clear parallelisms with information theory and opening new ways to model, compose, and (re)program advanced metasurfaces. This paper joins the reconfigurable and digital approaches, and presents a metasurface that leverages the tunability of graphene to perform beam steering at terahertz frequencies. A comprehensive design methodology is presented encompassing technological, unit cell design, digital metamaterial synthesis, and programmability aspects. By setting up and dynamically adjusting a phase gradient along the metasurface plane, the resulting device achieves beam steering at all practical directions. The proposed design is studied through analytical models and validated numerically, showing beam widths and steering errors well below 10 o and 5% in most cases. Finally, design guidelines are extracted through a scalability analysis involving the metasurface size and number of unit cell states.

On-chip communication remains as a key research issue at the gates of the manycore era. In response to this, novel interconnect technologies have opened the door to new Network-on-Chip (NoC) solutions towards greater scalability and architectural flexibility. Particularly, wireless on-chip communication has garnered considerable attention due to its inherent broadcast capabilities, low latency, and system-level simplicity. This work presents ORTHONOC, a wired-wireless architecture that differs from existing proposals in that both network planes are decoupled and driven by traffic steering policies enforced at the network interfaces. With these and other design decisions, ORTHONOC seeks to emphasize the ordered broadcast advantage offered by the wireless technology. The performance and cost of ORTHONOC are first explored using synthetic traffic, showing substantial improvements with respect to other wired-wireless designs with a similar number of antennas. Then, the applicability of ORTHONOC in the multiprocessor scenario is demonstrated through the evaluation of a simple architecture that implements fast synchronization via ordered broadcast transmissions. Simulations reveal significant execution time speedups and communication energy savings for 64-threaded benchmarks, proving that the value of ORTHONOC goes beyond simply improving the performance of the on-chip interconnect.

Graphene plasmonic antennas possess two significant features that render them appealing for short-range wireless communications, notably, inherent tunability and miniaturization due to the unique frequency dispersion of graphene and its support for surface plasmon waves in the terahertz band. In this letter, dipole-like antennas using few-layer graphene are proposed to achieve a better trade-off between miniaturization and radiation efficiency than current monolayer graphene antennas. The characteristics of few-layer graphene antennas are evaluated and then compared with those of antennas based on monolayer graphene and graphene stacks, which could also provide such improvements. To this end, first, the propagation properties of one-dimensional and two-dimensional plasmonic waveguides based on the aforementioned graphene structures are obtained by transfer matrix theory and finite-element simulation, respectively. Second, the antennas are investigated as three-dimensional structures using a full-wave solver. Results show that the highest radiation efficiency among the compared designs is achieved with the few-layer graphene, while the highest miniaturization is obtained with the even mode of the graphene stack antenna.

Quantum computing represents a paradigm shift in computation, offering the potential to solve complex problems intractable for classical computers. Although current quantum processors already consist of a few hundred qubits, their scalability remains a significant challenge. Modular quantum computing architectures have emerged as a promising approach to scale up quantum computing systems. This article delves into the critical aspects of distributed multi-core quantum computing, focusing on quantum circuit mapping, a fundamental task to successfully execute quantum algorithms across cores while minimizing inter-core communications. We derive the theoretical bounds on the number of non-local communications needed for random quantum circuits and introduce the Hungarian Qubit Assignment (HQA) algorithm, a multi-core mapping algorithm designed to optimize qubit assignments to cores with the aim of reducing inter-core communications. Our exhaustive evaluation of HQA against state-of-the-art circuit mapping algorithms for modular architectures reveals a 4.9× and 1.6× improvement in terms of execution time and non-local communications, respectively, compared to the best-performing algorithm. HQA emerges as a very promising scalable approach for mapping quantum circuits into multi-core architectures, positioning it as a valuable tool for harnessing the potential of quantum computing at scale.

Despite its tremendous potential, it is still unclear how quantum computing will scale to satisfy the requirements of its most powerful applications. Among other issues, there are hard limits to the number of qubits that can be integrated into a single chip. Multi-core architectures are a firm candidate for unlocking the scalability of quantum processors. Nonetheless, the vulnerability and complexity of quantum communications make this a challenging approach. A comprehensive design should imply consolidating the communications stack in the quantum computer architecture. In this paper, we explain how this vision, by entangling communications and computation in the core of the design, may help to solve the open challenges. We also summarize the first results of our application of structured design methodologies backing this vision. With our work, we hope to contribute with design guidelines that may help unleash the potential of quantum computing.