A systematic comparison of flipped voltage followers circuits is presented. Two new versions of the flipped voltage follower are introduced. They are characterized by very low output impedance, high bandwidth speed, wide signal swing. All structures can be easily modified for class AB operation. Simulation results show that the newly introduced structures have optimal characteristics

A current-mode capacitor multiplier using a differential amplifier with exponential current scaling is presented. The proposed circuit consists of a reduced implementation of a multiplier based on differential amplifiers with decreased need for parameter matching compared with a conventional structure, thus reducing the power consumption and silicon area. It includes an exponential current scaling scheme to provide a large multiplication factor. Additionally, the differential input stage offers the capability to implement a floating realization for bidirectional applications. The circuit operates with a minimum supply of a gate-source voltage and two saturation voltages of a transistor, making it suitable for low-voltage applications. Experimental results from a fabricated prototype in 0.5-μm technology show the operation of the grounded and floating realizations, as well as their performance when implemented in a second-order low-pass analog filter.

With the aggressive scaling of transistor dimensions, intrinsic device gains are dropping but the need for high-gain amplifiers still exists, resulting in a great interest in multi-stage amplifiers. Most existing amplifier topologies rely on Miller capacitors which achieve stability at the expense of reduced speed. In this paper, a new state feedback compensation strategy with gain enhancement using partial positive feedback is proposed whereby a multistage amplifier can be made output-compensated, thereby requiring no Miller capacitance while being able to drive a wide range of load capacitances. After a thorough theoretical analysis, a topology prototype is fabricated in a standard 130 nm CMOS technology and is able to drive loads from 90 nF-50 nF (~555x) using three discrete modes. The amplifier's power and bandwidth are scalable depending on the expected capacitive load range, with a maximum power consumption of (185μW) from a 1V supply. Comparison with state-of-the-art amplifiers shows superior small-signal performance and competitive large-signal performance while driving a significantly larger range of capacitive loads.

A capacitor multiplier realization based on current-voltage conversion with a high-performance voltage follower is presented. The architecture has a large multiplication factor of up to 10 000 or larger compared with current-mode multipliers, and a wide dynamic range compared with voltage-mode capacitor multipliers. It offers higher accuracy than voltage-mode multipliers as the design is based on passive devices, eliminating the variations of the drain-source output resistance of a transistor. The structure offers a very low equivalent series resistance, and it proved to be useful for low-voltage applications. Experimental results of a test chip in 0.5-μm CMOS technology implemented in low-pass and bandpass filters that validate the operation are presented.

A new configuration of the flipped voltage follower (FVF) offering class‐AB operation is presented. The idea uses a bulk‐driven transistor instead of the constant current source of the typical FVF topology. This feature enhances the sourcing capability for class‐AB operation and the symmetrical slew rate. The key element is changing the basic structure of the original FVF circuit with no additional devices. A detailed analysis of the circuit and simulations using Spice are presented. The experimental results from a manufactured circuit prototype using CMOS 0.35 μm technology demonstrate the feasibility of the proposal.

A current-mode capacitor multiplier using a high performance voltage follower is presented. The architecture has the ability to balance between very low equivalent series resistance of a few tens of ohms due to the voltage follower and very low power consumption achieved by means of reducing the biasing current in the output devices, forcing them to operate in subthreshold during static conditions, which, in consequence, results in an increased parallel load resistance. Analysis shows that one corner frequency is shifted by the gain factor of a transistor as an amplifying device, thus increasing the frequency range of operation. This is achieved with very few additional devices and without compromising accuracy. The architecture of a floating equivalent capacitor is also presented. Experimental results of a prototype chip fabricated in 0.5- μm CMOS technology show the operation of the proposed circuits used in an low-pass, high-pass, and notch filters.