Arguably, SiC technology is the most rapidly expanding IC manufacturing technology driven mostly by the aggressive roadmap for battery electric vehicle penetration and also industrial high-voltage/high-power applications. This paper provides a comprehensive overview of the state of the art of SiC technology focusing on the challenges starting from the difficult and lengthy SiC substrate growth all the way to the complex MOSFET assembly processes. We focus on the differentiation from the established Si manufacturing processes and provide a comprehensive list of references as well as a brief description of our own research into the key manufacturing processes in this technology. We also present a SiC technology and product roadmap.

In this work, we report fabrication and characterization of high breakdown voltage and high current injection vertical gallium nitride (GaN)-on-GaN p-n diodes with an etched mesa structure with guard rings termination on ammonothermally grown bulk GaN substrates. Bright electroluminescence from active region under forward bias was observed with high intensity near band edge emission and low intensity defect and unintentional impurities-related bands. Fabricated devices were characterized by a high breakdown voltage up to 1940 V, a high on/off current ratio over 10 $^{\text{13}}$ , a high current density above 10 kA/cm $^\text{2}$ , and an extremely low ON-resistance below 0.1 m $\Omega$ cm $^\text{2}$ under high current injection.

The electrical and physical properties of the SiC/SiO₂ interfaces are critical for the reliability and performance of SiC-based MOSFETs. Optimizing the oxidation and post-oxidation processes is the most promising method of improving oxide quality, channel mobility, and thus the series resistance of the MOSFET. In this work, we analyze the effects of the POCl₃ annealing and NO annealing processes on the electrical properties of metal–oxide–semiconductor (MOS) devices formed on 4H-SiC (0001). It is shown that combined annealing processes can result in both low interface trap density (D_it), which is crucial for oxide application in SiC power electronics, and high dielectric breakdown voltage comparable with those obtained via thermal oxidation in pure O₂. Comparative results of non-annealed, NO-annealed, and POCl₃-annealed oxide–semiconductor structures are shown. POCl₃ annealing reduces the interface state density more effectively than the well-established NO annealing processes. The result of 2 × 10¹¹ cm⁻² for the interface trap density was attained for a sequence of the two-step annealing process in POCl₃ and next in NO atmospheres. The obtained values D_it are comparable to the best results for the SiO₂/4H-SiC structures recognized in the literature, while the dielectric critical field was measured at a level ≥9 MVcm⁻¹ with low leakage currents at high fields. Dielectrics, which were developed in this study, have been used to fabricate the 4H-SiC MOSFET transistors successfully.

Purpose: This paper aims to investigate the sintering and solid liquid interdiffusion bonding (SLID) techniques to attach AlGaN/GaN-on-Si chips to direct bond copper (DBC) substrate. The influence of metal layers deposited on the backside of AlGaN/GaN-on-Si dies on the assembly process is also investigated.Design/methodology/approach: The authors assumed the value of the shear strength to be a basic parameter for evaluation of mechanical properties. Additionally, the surface condition after shearing was assessed by SEM photographs and the shear surface was studied by X-ray diffraction method. The SLID requires Sn-plated DBC substrate and can be carried out at temperature slightly higher than 250°C and pressure reduced to 4 MPa, while the sintering requires process temperature of 350°C and the pressure at least 7.5 MPa.Findings: Ag-, Au-backside covered high electron mobility transistor (HEMT) chips can be assembled on Sn-plated DBC substrates by SLID technology. In case of sintering technology, Cu- or Ag-backside covered HEMT chips can be assembled on Ag- or Ni/Au-plated DBC substrates. The SLID process can be realized at lower temperature and decreased pressure than sintering process.Research limitations/implications: For SLID technology, the adhesion between Cu-backside covered HEMT die and DBC with Sn layer loses its operational properties after short-term ageing in air at temperature of 300°C.Originality/value: In the SLID process, Sn-Cu and Sn-Ag intermetallic compounds and alloys are responsible for creation of the joint between Sn-plated DBC and micropowder Ag layer, while the sintered joint between the chip and Ag-based micropowder is formed in diffusion process.