Mariusz Sochacki

Prof. Mariusz Sochacki

Institute of Microelectronics and Optoelectronics, Warsaw University of Technology, Koszykowa 75, 00-662 Warsaw, Poland
orcid

Research Focus & Metrics

Academic Career Length

7Years (2020-Present)

(Calculated once Scilit publication data is synced: current year − year of first publication + 1)

Representative Publications

View All Publications
24 December 2021 in Materials
Verified
Journal Article
Open access
PDF file
KRKatarzyna Racka-Szmidt
Katarzyna Racka-Szmidt
BSBartłomiej Stonio
Bartłomiej Stonio
JŻJarosław Żelazko
Jarosław Żelazko
MFMaciej Filipiak
Maciej Filipiak
MSMariusz Sochacki
Mariusz Sochacki
The inductively coupled plasma reactive ion etching (ICP-RIE) is a selective dry etching method used in fabrication technology of various semiconductor devices. The etching is used to form non-planar microstructures—trenches or mesa structures, and tilted sidewalls with a controlled angle. The ICP-RIE method combining a high finishing accuracy and reproducibility is excellent for etching hard materials, such as SiC, GaN or diamond. The paper presents a review of silicon carbide etching—principles of the ICP-RIE method, the results of SiC etching and undesired phenomena of the ICP-RIE process are presented. The article includes SEM photos and experimental results obtained from different ICP-RIE processes. The influence of O2 addition to the SF6 plasma as well as the change of both RIE and ICP power on the etching rate of the Cr mask used in processes and on the selectivity of SiC/Cr etching are reported for the first time. SiC is an attractive semiconductor with many excellent properties, that can bring huge potential benefits thorough advances in submicron semiconductor processing technology. Recently, there has been an interest in SiC due to its potential wide application in power electronics, in particular in automotive, renewable energy and rail transport.

24 December 2024 in Materials
Verified
Journal Article
Open access
PDF file
MKMaciej Kaminski
Maciej Kaminski
KKKrystian Król
Krystian Król
NKNorbert Kwietniewski
Norbert Kwietniewski
MMMarcin Myśliwiec
Marcin Myśliwiec
MSMariusz Sochacki
Mariusz Sochacki
ASAndrzej Strojwas
Andrzej Strojwas
Arguably, SiC technology is the most rapidly expanding IC manufacturing technology driven mostly by the aggressive roadmap for battery electric vehicle penetration and also industrial high-voltage/high-power applications. This paper provides a comprehensive overview of the state of the art of SiC technology focusing on the challenges starting from the difficult and lengthy SiC substrate growth all the way to the complex MOSFET assembly processes. We focus on the differentiation from the established Si manufacturing processes and provide a comprehensive list of references as well as a brief description of our own research into the key manufacturing processes in this technology. We also present a SiC technology and product roadmap.

11 February 2020 in Journal of Applied Physics
Verified
Journal Article
Closed access
PDF file
ŁGŁ. Gelczuk
Ł. Gelczuk
MDM. Dąbrowska-Szata
M. Dąbrowska-Szata
VKVl. Kolkovsky
Vl. Kolkovsky
MSMariusz Sochacki
Mariusz Sochacki
JSJan Szmidt
Jan Szmidt
TGTeodor Gotszalk
Teodor Gotszalk
Several deep level defects were observed by conventional deep level transient spectroscopy (DLTS) and high-resolution Laplace DLTS (LDLTS) in n-type 4H-SiC junction barrier Schottky diodes. We have shown that the broad DLTS peak labeled Z1/2 has, in fact, two components, Z1 and Z2, with activation enthalpies for electron emission of 0.63 eV and 0.68 eV, respectively. The reorientation process between these two components was observed. A combination of double-correlated DLTS and LDLTS demonstrated an anomalous reduction of the emission rate and an increase of the activation enthalpy of Z2 with an increase of the reverse bias applied to the diode. The possible explanation of this phenomenon could be correlated with a tensile stress in epitaxial SiC layers. The results observed are discussed in the frame of the model that correlates Z1 and Z2 with carbon vacancies (VC), located at hexagonal (h) and cubic (k) lattice sites, respectively. We also discussed the origin of other traps E0–E5 with particular emphasis on a N-related shallow donor level located at 0.04 eV below the conduction band, which has never been previously reported by DLTS studies.

22 July 2020 in Circuit World
Verified
Journal Article
Closed access
RKRyszard Kisiel
Ryszard Kisiel
Marek GuziewiczMarek Guziewicz
Marek Guziewicz
ATAndrzej Taube
Andrzej Taube
MKMaciej Kaminski
Maciej Kaminski
MSMariusz Sochacki
Mariusz Sochacki
Purpose: This paper aims to investigate the sintering and solid liquid interdiffusion bonding (SLID) techniques to attach AlGaN/GaN-on-Si chips to direct bond copper (DBC) substrate. The influence of metal layers deposited on the backside of AlGaN/GaN-on-Si dies on the assembly process is also investigated.Design/methodology/approach: The authors assumed the value of the shear strength to be a basic parameter for evaluation of mechanical properties. Additionally, the surface condition after shearing was assessed by SEM photographs and the shear surface was studied by X-ray diffraction method. The SLID requires Sn-plated DBC substrate and can be carried out at temperature slightly higher than 250°C and pressure reduced to 4 MPa, while the sintering requires process temperature of 350°C and the pressure at least 7.5 MPa.Findings: Ag-, Au-backside covered high electron mobility transistor (HEMT) chips can be assembled on Sn-plated DBC substrates by SLID technology. In case of sintering technology, Cu- or Ag-backside covered HEMT chips can be assembled on Ag- or Ni/Au-plated DBC substrates. The SLID process can be realized at lower temperature and decreased pressure than sintering process.Research limitations/implications: For SLID technology, the adhesion between Cu-backside covered HEMT die and DBC with Sn layer loses its operational properties after short-term ageing in air at temperature of 300°C.Originality/value: In the SLID process, Sn-Cu and Sn-Ag intermetallic compounds and alloys are responsible for creation of the joint between Sn-plated DBC and micropowder Ag layer, while the sintered joint between the chip and Ag-based micropowder is formed in diffusion process.

3 July 2024 in Energies
Verified
Journal Article
Open access
PDF file
PFPiotr Firek
Piotr Firek
ECElzbieta Maria Czerwosz
Elzbieta Maria Czerwosz
HWHalina Wronka
Halina Wronka
SKSławomir Krawczyk
Sławomir Krawczyk
MKMirosław Kozłowski
Mirosław Kozłowski
JSJan Szmidt
Jan Szmidt
The objective of this paper is to evaluate the effect of a nanostructured C-Pd film deposited in the gate area of a field-effect transistor (FET) with a carbon–palladium composite gate (C-Pd/FET) on the hydrogen-sensing properties of the transistor. The method of preparing a field-effect transistor (FET) with a C-Pd film deposited as a gate and the properties of such a transistor and the film itself are presented. The C-Pd film deposited by PVD method on the gate area serves as an active layer. The PVD process was carried out in a dynamic vacuum of 10−5 mbar from two separated sources—one containing fullerenes (C60) and the other containing palladium acetate. Scanning electron microscopy (SEM), energy-dispersive X-ray spectroscopy (EDS, EDX) and electrical property studies were used to the characterize C-Pd films and FET/C-Pd structures. SEM observations revealed the topography of C-Pd films and FET/C-Pd transistors. EDS/EDX microanalysis was applied to visualize the arrangement of elements on the studied surfaces. The changes in electrical properties (resistance and relative resistance) due to the presence of hydrogen were studied in a designed and computerized experimental set-up. The enhanced properties of the FET/C-Pd transistor are demonstrated in terms of hydrogen detection.