Arguably, SiC technology is the most rapidly expanding IC manufacturing technology driven mostly by the aggressive roadmap for battery electric vehicle penetration and also industrial high-voltage/high-power applications. This paper provides a comprehensive overview of the state of the art of SiC technology focusing on the challenges starting from the difficult and lengthy SiC substrate growth all the way to the complex MOSFET assembly processes. We focus on the differentiation from the established Si manufacturing processes and provide a comprehensive list of references as well as a brief description of our own research into the key manufacturing processes in this technology. We also present a SiC technology and product roadmap.

The electrical and physical properties of the SiC/SiO₂ interfaces are critical for the reliability and performance of SiC-based MOSFETs. Optimizing the oxidation and post-oxidation processes is the most promising method of improving oxide quality, channel mobility, and thus the series resistance of the MOSFET. In this work, we analyze the effects of the POCl₃ annealing and NO annealing processes on the electrical properties of metal–oxide–semiconductor (MOS) devices formed on 4H-SiC (0001). It is shown that combined annealing processes can result in both low interface trap density (D_it), which is crucial for oxide application in SiC power electronics, and high dielectric breakdown voltage comparable with those obtained via thermal oxidation in pure O₂. Comparative results of non-annealed, NO-annealed, and POCl₃-annealed oxide–semiconductor structures are shown. POCl₃ annealing reduces the interface state density more effectively than the well-established NO annealing processes. The result of 2 × 10¹¹ cm⁻² for the interface trap density was attained for a sequence of the two-step annealing process in POCl₃ and next in NO atmospheres. The obtained values D_it are comparable to the best results for the SiO₂/4H-SiC structures recognized in the literature, while the dielectric critical field was measured at a level ≥9 MVcm⁻¹ with low leakage currents at high fields. Dielectrics, which were developed in this study, have been used to fabricate the 4H-SiC MOSFET transistors successfully.