Model Predictive Control (MPC) has emerged as a promising alternative for controlling power converters, offering benefits such as flexibility, simplicity, and rapid control response, particularly when short-horizon algorithms are employed. This paper introduces a system using a short-horizon Finite Control Set MPC (FCS-MPC) strategy to specifically address the challenge of non-minimum phase behavior in boost converters. The non-minimum phase issue, which complicates the control process by introducing an initial inverse response, is effectively mitigated by the proposed method. A Proportional–Integral (PI) controller is integrated to dynamically adjust the reference current based on the output voltage error, thereby enhancing overall system stability and performance. Unlike conventional PI-MPC methods, where the PI controller has an influence on the system dynamics, the PI controller in this approach is solely used for tuning the reference current needed for the FCS-MPC controller. The PI controller addresses small deviations in output voltage, primarily due to model prediction inaccuracies, ensuring steady-state accuracy, while the FCS-MPC handles fast dynamic responses to adapt the controller’s behavior based on load conditions. This dual control strategy effectively balances the need for precise voltage regulation and rapid adaptation to varying load conditions. The proposed method’s effectiveness is validated through a multi-stage simulation test, demonstrating significant improvements in response time and stability compared to traditional control methods. Hardware-in-the-loop testing further confirms the system’s robustness and potential for real-time applications in power electronics.

Model Predictive Control (MPC) is widely adopted for power electronics converters due to its ability to optimize system performance under dynamic constraints. However, its FPGA implementation remains challenging due to the complexity of Hardware Description Language (HDL) programming. This paper addresses this challenge by introducing a straightforward methodology that simplifies FPGA implementation using MATLAB R2022b Simulink HDL Coder. It is shown that HDL Coder yields favorable synthesis outcomes, both in terms of area and time, compared to hand-coded HDL. Notably, the proposed method achieves a significantly reduced sampling step for the MPC algorithm—down to 32 ns—marking a substantial improvement over state-of-the-art implementations. The Integrated Logic Analyzer (ILA) IP available in the Vivado tool is used during the HIL testing phase to facilitate the real-time observation and analysis required for debugging and confirming the FPGA-implemented controller performance. Additionally, this paper discusses the advantages of utilizing HDL Coder for simplifying the FPGA programming process in power electronics applications and addresses the design challenges encountered using this methodology.

Recent advancements in FPGA technology have made these devices a cost-effective alternative for implementing Model Predictive Controllers (MPCs). This paper addresses the fast prototyping of FPGA-based Finite Control Set (FCS)-MPCs and the essential verification process preceding hardware-level testing. The methodology leverages MATLAB HDL Coder for automated HDL code generation. This approach offers a streamlined process and eliminates the need for expertise in hand-coded HDL, making it an ideal solution for power electronics engineers. The approach is exemplified using a three-phase active neutral point clamped converter. Beyond presenting the design approach, the paper introduces a systematic multi-stage verification process essential for the rapid prototyping of FCS-MPC controllers. This verification involves step-by-step simulations followed by experimental hardware-in-the-loop tests, ensuring the reliability of each stage for the smooth transition from pure simulation to FPGA hardware implementation of the controller. The proposed methodology not only simplifies the implementation and testing of the MPC algorithm within an FPGA but also facilitates the debugging process, a crucial aspect of the design phase.