This paper aims to compare different design alternatives of hardware-in-the-loop (HIL) for emulating power converters in Field Programmable Gate Arrays (FPGAs). It proposes various numerical formats (fixed and floating-point) and different approaches (pure VHSIC Hardware Description Language (VHDL), Intellectual Properties (IPs), automated MATLAB HDL code, and High-Level Synthesis (HLS)) to design power converters. Although the proposed models are simple power electronics HIL systems, the idea can be extended to any HIL system. This study compares the design effort of different coding methods and numerical formats considering possible synthesis tools (Precision and Vivado), and it comprises an analytical discussion in terms of area and speed. The different models are synthesized as ad-hoc modules in general-purpose FPGAs, but also using the NI myRIO device as an example of a commercial tool capable of implementing HIL models. The comparison confirms that the optimum design alternative must be chosen based on the application (complexity, frequency, etc.) and designers’ constraints, such as available area, coding expertise, and design effort.

Nowadays, the Hardware-In-the-Loop (HIL) technique is widely used to test different power electronic converters. These real-time simulations require processing large data at high speed, which makes this application very suitable for FPGAs (Field Programmable Gate Array) as they are capable of parallel processing. This paper provides an analytical discussion on three HIL models for a full-bridge converter. The three models use different possible numerical formats, namely float and fixed-point, the latter with and without optimizing the width of signals to the embedded DSP (Digital Signal Processors) blocks of the FPGA. The optimized fixed-point model (OFPM) uses three and two times fewer DSP blocks or LUTs (Look Up Tables), and the maximum achievable clock frequency is also up to 35 % and 25 % higher than the float model and non-optimized fixed-point model (nOFPM), respectively. Furthermore, the models’ accuracy is proportional to the clock frequency, thus the OFPM is also the most accurate model. Finally, the paper shows the differences in the simulation when the models include or not losses, proving that not including losses leads to high errors, especially during transients.

Model Predictive Control (MPC) has emerged as a promising alternative for controlling power converters, offering benefits such as flexibility, simplicity, and rapid control response, particularly when short-horizon algorithms are employed. This paper introduces a system using a short-horizon Finite Control Set MPC (FCS-MPC) strategy to specifically address the challenge of non-minimum phase behavior in boost converters. The non-minimum phase issue, which complicates the control process by introducing an initial inverse response, is effectively mitigated by the proposed method. A Proportional–Integral (PI) controller is integrated to dynamically adjust the reference current based on the output voltage error, thereby enhancing overall system stability and performance. Unlike conventional PI-MPC methods, where the PI controller has an influence on the system dynamics, the PI controller in this approach is solely used for tuning the reference current needed for the FCS-MPC controller. The PI controller addresses small deviations in output voltage, primarily due to model prediction inaccuracies, ensuring steady-state accuracy, while the FCS-MPC handles fast dynamic responses to adapt the controller’s behavior based on load conditions. This dual control strategy effectively balances the need for precise voltage regulation and rapid adaptation to varying load conditions. The proposed method’s effectiveness is validated through a multi-stage simulation test, demonstrating significant improvements in response time and stability compared to traditional control methods. Hardware-in-the-loop testing further confirms the system’s robustness and potential for real-time applications in power electronics.

Model Predictive Control (MPC) is widely adopted for power electronics converters due to its ability to optimize system performance under dynamic constraints. However, its FPGA implementation remains challenging due to the complexity of Hardware Description Language (HDL) programming. This paper addresses this challenge by introducing a straightforward methodology that simplifies FPGA implementation using MATLAB R2022b Simulink HDL Coder. It is shown that HDL Coder yields favorable synthesis outcomes, both in terms of area and time, compared to hand-coded HDL. Notably, the proposed method achieves a significantly reduced sampling step for the MPC algorithm—down to 32 ns—marking a substantial improvement over state-of-the-art implementations. The Integrated Logic Analyzer (ILA) IP available in the Vivado tool is used during the HIL testing phase to facilitate the real-time observation and analysis required for debugging and confirming the FPGA-implemented controller performance. Additionally, this paper discusses the advantages of utilizing HDL Coder for simplifying the FPGA programming process in power electronics applications and addresses the design challenges encountered using this methodology.