Traditional GaN HEMTs on silicon suffer relatively low lateral and vertical blocking voltages and thick buffers, which impede their use in $\boldsymbol {\ge }1.2$ -kV applications. In this work, the prototypes of 8-kV GaN HEMTs on 6-in sapphire are successfully fabricated using CMOS-compatible processing. An etch-stop nitride layer AlN in the in situ SiN cap precisely defines the gate dielectric thickness. Au-free low-temperature ohmic contact and metal I are achieved by Ti/AlCu/Ti/TiN, and gate metal is achieved by TiN/Ti/AlCu/Ti/TiN, which significantly reduces the material cost. The high mechanical strength of sapphire results in low nonuniformity and well-controlled warpage, enabling the use of a 1.5- $\boldsymbol {\mu }$ m buffer. The fabricated HEMTs with an ${L}_{\text {GD}}$ of $100~\boldsymbol {\mu }$ m exhibit a low ${R}_{\text {ON}}$ of $52~\boldsymbol {\Omega } \cdot $ mm and a stable ${V}_{\text {TH}}$ of −20 V. Benefiting from high-quality in situ SiN passivation, the dynamic ${R}_{\text {ON}}$ and ${V}_{\text {TH}}$ shift are maintained within 2.5% and 10%, respectively. The OFF-state breakdown voltage (BV) is increased beyond 8 kV using a simple device structure with only two field plates. The proposed low-cost and CMOS-compatible 8-kV GaN HEMTs fabricated on 6-in sapphire highlight an extremely simple epitaxy process, lateral device structure, and processing flow. Therefore, they offer great potential for serving future medium-voltage applications.

The two crucial factors of large scale and high voltage can hardly be balanced for the traditional GaN HEMTs on Si substrates. Recently, one promising solution, GaN-on-sapphire, has attracted great attention. However, the commercialized GaN-on-sapphire wafers ever reported are usually 6 in. It is urgent to develop 8-in GaN-on-sapphire to reduce the cost and meet the market demands. In this work, to the best of our knowledge, an 8-in GaN-on-sapphire wafer is demonstrated for the first time. The sheet resistance $\textit{R}_{{\Box}} $ exhibits a wafer-level nonuniformity of 4% and an average value of 310 $\bm\Omega/\Box$ , and the warpage is kept to 30 $\mu $ m, by dedicatedly tuning the 1.98- $\mu $ m buffer stack. The fabricated 200-V HEMTs exhibit a low $\textit{R}_{\biosc{on}}$ of 6.5 $\bm\Omega \cdot\text{mm}$ , a $\textit{V}_{\text{TH}}$ of $-$ 4.2 V, and an OFF-state breakdown voltage above 500 V without any field plate. The electrical mapping visualizes $\textit{R}_{\biosc{on}}$ and $\textit{V}_{\text{TH}}$ distributed in concentric circles across the wafer. Generally, this work demonstrates the feasibility of realizing 8-in GaN-on-sapphire for power electronics applications in the future.

In this work, we demonstrated the epitaxial growth of a gallium nitride (GaN) buffer structure on 200 mm SOI (silicon-on-insulator) substrates. This epitaxial layer is grown using a reversed stepped superlattice buffer (RSSL), which is composed of two superlattice (SL) layers with different Al component ratios stacked in reverse order. The upper layer, with a higher Al component ratio, introduces tensile stress instead of accumulative compressive stress and reduces the in situ curvature of the wafer, thereby achieving a well-controlled wafer bow ≤ ±50 µm for a 3.3 µm thick buffer. Thanks to the compliant SOI substrate, good crystal quality of the grown GaN layers was obtained, and a breakdown voltage of 750 V for a 3.3 µm thick GaN buffer was achieved. The breakdown field strength of the epitaxial GaN buffer layer on the SOI substrate is estimated to be ~2.27 MV/cm, which is higher than the breakdown field strength of the GaN-on-Si epitaxial buffer layer. This RSSL buffer also demonstrated a low buffer dispersion of less than 10%, which is good enough for the further processing of device and circuit fabrication. A D-mode GaN HEMT was fabricated on this RSSL buffer, which showed a good on/off ratio of ~10⁹ and a breakdown voltage of 450 V.