The development of high-performance oxide-based transistors is critical to enable very large-scale integration (VLSI) of monolithic 3-D integrated circuit (IC) in complementary metal oxide semiconductor (CMOS) backend-of-line (BEOL). Atomic layer deposition (ALD) deposited ZnO is an attractive candidate due to its excellent electrical properties, low processing temperature below copper interconnect thermal budget, and conformal sidewall deposition for novel 3D architecture. An optimized ALD deposited ZnO thin-film transistor achieving a record field-effect and intrinsic mobility (µ_FE /µ_o) of 85/140 cm²/V·s is presented here. The ZnO TFT was integrated with HfO₂ RRAM in a 1 kbit (32 × 32) 1T1R array, demonstrating functionalities in RRAM switching. In order to co-design for future technology requiring high performance BEOL circuitries implementation, a spice-compatible model of the ZnO TFTs was developed. We then present designs of various ZnO TFT-based inverters, and 5-stage ring oscillators through simulations and experiments with working frequency exceeding 10’s of MHz.

Multi-valued logics (MVLs) offer higher information density, reduced circuit and interconnect complexity, lower power dissipation, and faster speed over conventional binary logic system. Recent advancement in MVL research, particularly with emerging low-dimensional materials, suggests that breakthroughs may be imminent if multistates transistors can be fabricated controllably for large-scale integration. Here, a concept of source-gating transistors (SGTs) is developed and realized using carbon nanotubes (CNTs). By extending the source electrode into the channel of conventional CNT transistors, a controllable p-n homojunction is formed, allowing CNT-SGTs to reliably switch between three distinct states. Capitalizing on the straightforward fabrication process of CNT-SGTs, ternary inverters, NMIN and NMAX logic gates, ternary SRAM cells, and a ternary neural network achieving 100% image classification accuracy have been successfully implemented. This study represents the most advanced and highest-performing ternary circuits realized with low-dimensional materials to date. This progress highlights the potential of CNT-SGTs in driving the future of MVL architectures.

Digital-driven scaling poses significant problems to analog circuits because scaling severely deteriorates transistor current saturation, significantly degrading the intrinsic gain. Special material properties of emerging low-dimensional semiconductors trigger the possibility of providing solutions. We report complementary carbon nanotube thin-film transistors with negative differential resistance-induced current super-saturation for high, exponentially variable intrinsic gain with immunity against degradation during scaling. Current super-saturation at the negative-to-positive differential resistance transition boundary provides intrinsic gain singularities. The large-window, gate-modulated negative differential resistance behavior derived from carbon nanotube’s characteristics enables its practical utilization in circuits. When approaching the singularity, we record that the intrinsic gain varies by orders of magnitude, ranging from 10² to 10⁶ at different operation points. We further demonstrate high and exponentially variable gain in an operational amplifier, showing a tunable single-stage gain ranging from 35 to 60 decibels.

The creation of carbon nanotubes has sparked a paradigm shift in the post-silicon era because of their decent electronic and optical properties. However, interface traps pose an obstacle in the realization of high-performance carbon nanotube field-effect transistors (CNTFETs). Herein, we systematically investigate the C−V characteristics of CNTFETs and propose a small-signal equivalent model to decouple the effects arising from interface traps. Moreover, intrinsic parameters associated with interface traps can be feasibly extracted using this approach. An analytical capacitance model is further developed to be incorporated into the well-established CNTFET virtual source model, and excellent agreement has been achieved between our simulation and the measured results of the as-fabricated MOSCAP. The models developed here help to gain insight into the physical properties of high-κ dielectric interface traps subjected to different processes and inform strategies to achieve high-performance CNTFETs.

Growing research interests are being devoted to the monolithic integration of complementary field effect transistors (CFETs), which promise aggressive footprint reduction and improved performance. However, the bottom transistor usually suffers from poor immunity to short channel effects (SCEs), such as a degraded subthreshold swing. The presence of the substrate capacitance imposes a penalty on the electrostatic integrity for the bottom transistor, yielding asymmetric boundary conditions for each component of CFETs. Herein, MoS 2 and MoTe 2 are assembled as the n- and p-type channel materials respectively, and the characteristic length models for each type of transistor in a CFET are proposed to elucidate the unbalanced immunity to SCEs, stemming from the non-identical dielectric environment that they experience. The derived surface potential exhibits an excellent agreement with technology computer-aided design simulations. Furthermore, the effect of characteristic length on the static and dynamic behavior of CFET circuits is systematically studied. To mitigate parasitic effects, we introduce the silicon nitride spacer into CFETs, which is demonstrated to play a pivotal role in implementing high-performant integrated circuits by suppressing the fringe capacitance. The oscillation frequency of CFET with spacer reaches up to 160 MHz at a supply voltage of 2 V, with 2× improvement compared to the one without spacer. This work highlights the role of substrate in curbing the scaling capability of CFETs and offers design guidelines about material screening, stacking strategy, and structure optimization to enable the scaling and performance enhancement of CFETs at both transistor and circuit levels.

The development of oxide semiconductor devices for monolithic 3D (M3D) integration has largely remained at the device level, limiting progress toward large‐scale applications. To advance this technology, evaluation from device to circuit level—akin to CMOS—is essential. This work presents a comprehensive study of M3D‐compatible technology using indium‐gallium‐zinc oxide (IGZO) thin‐film transistors (TFTs) fabricated via plasma‐enhanced atomic layer deposition (PEALD). The investigation spans material characterization, device performance, technology computer‐aided design (TCAD) Modeling, circuit design, and scaling projections. At device level, comprehensive material and electrical characterizations elucidate intrinsic property interdependencies in IGZO TFTs, which exhibit a field‐effect mobility ( µ _FE ) up to 116.35 cm ² V ⁻¹ ·s ⁻¹ , high reliability (△ V _TH < 0.15 V), and low variation (△ µ _FE < 2%). These results enable accurate TCAD models for system‐level co‐design of unipolar TFT circuits, including pseudo‐CMOS inverters, 5‐stage ring oscillators (ROs), and static random‐access memory (SRAM) cells, all exhibiting robust functionality. For future technology scaling, projections to the 22 nm node show RO frequencies up to 240 MHz and SRAM switching times as low as 0.78 ns, with strong dynamic and noise characteristics. This work offers critical insight into circuit‐level performance of PEALD IGZO TFTs and provides valuable guidance for the implementation of oxide semiconductor‐based M3D systems.