In this paper, we share our practical experience gained during the development of CMOS-MEMS (Complementary Metal-Oxide Semiconductor Micro Electro Mechanical Systems) devices in IHP SG25 technology. The experimental prototyping process is illustrated with examples of three CMOS-MEMS chips and starts from rough process exploration and characterization, followed by the definition of the useful MEMS design space to finally reach CMOS-MEMS devices with inertial mass up to 4.3 $\mathsf{\mu }$g and resonance frequency down to 4.35 kHz. Furthermore, the presented design techniques help to avoid several structural and reliability issues such as layer delamination, device stiction, passivation fracture or device cracking due to stress.

Designing of MEMS devices requires modeling step. Many devices combines mechanical and electrical domains. Very often it is desired to use one simulation tool that allows taking into account both domains. Such functionality has CADENCE environment. In this paper we do such simulations using developed macro model of capacitive MEMS accelerometer. The accelerometer is described in Verilog-A language and placed in electrical schematic that consist of read-out circuit. The simulations were performed for the device z-axis CMOS-integrated acceleration sensor that has been developed in UPC Barcelona. The results of simulations were compared to those obtained by measurements of fabricated device.

In this paper we present to the best of our knowledge a first ever reported CMOS BEOL-embedded lateral acceleration sensor obtained by simple isotropic inter-metal dielectric etching without any additional substrate etching steps. The device leverages the availability of thick metal and via layers of a 0.25 μm RF CMOS technology, featuring 7.36 kHz resonance frequency and differential capacitive sensitivity 0.2 fF/G. The accelerometer is monolithically integrated with on-chip sensing electronics exhibiting 200 μG/√Hz total noise floor at 2.5 V power supply and 550 μA current consumption.

In this paper we present a fully CMOS-compatible circuit that extends the weak-inversion exponential characteristic of a MOS transistor to seven decades of current. This circuit can be used to implement log-domain or translinear circuits up to the strong inversion region, allowing highly-accurate implementations of translinear loop functions and higher biasing currents (and potentially higher frequency operation) than MOS weak-inversion biased log-domain circuits.

A novel sampling scheme for coarse-fine time-to-digital converters (TDCs), whose architecture commonly comprises a synchronous counter as a coarse part and delay-line based phase interpolator as a fine part, is proposed. The presented approach eliminates any error in the coarse counter and is superior in terms of mean time between failures as well as complexity, area and power consumption in comparison to previously reported solutions.