Less than thirty years after the giant magnetoresistance (GMR) effect was described, GMR sensors are the preferred choice in many applications demanding the measurement of low magnetic fields in small volumes. This rapid deployment from theoretical basis to market and state-of-the-art applications can be explained by the combination of excellent inherent properties with the feasibility of fabrication, allowing the real integration with many other standard technologies. In this paper, we present a review focusing on how this capability of integration has allowed the improvement of the inherent capabilities and, therefore, the range of application of GMR sensors. After briefly describing the phenomenological basis, we deal on the benefits of low temperature deposition techniques regarding the integration of GMR sensors with flexible (plastic) substrates and pre-processed CMOS chips. In this way, the limit of detection can be improved by means of bettering the sensitivity or reducing the noise. We also report on novel fields of application of GMR sensors by the recapitulation of a number of cases of success of their integration with different heterogeneous complementary elements. We finally describe three fully functional systems, two of them in the bio-technology world, as the proof of how the integrability has been instrumental in the meteoric development of GMR sensors and their applications.

In this paper, we share our practical experience gained during the development of CMOS-MEMS (Complementary Metal-Oxide Semiconductor Micro Electro Mechanical Systems) devices in IHP SG25 technology. The experimental prototyping process is illustrated with examples of three CMOS-MEMS chips and starts from rough process exploration and characterization, followed by the definition of the useful MEMS design space to finally reach CMOS-MEMS devices with inertial mass up to 4.3 $\mathsf{\mu }$g and resonance frequency down to 4.35 kHz. Furthermore, the presented design techniques help to avoid several structural and reliability issues such as layer delamination, device stiction, passivation fracture or device cracking due to stress.

This article presents several design techniques to fabricate micro-electro-mechanical systems (MEMS) using standard complementary metal-oxide semiconductor (CMOS) processes. They were applied to fabricate high yield CMOS-MEMS shielded Lorentz-force magnetometers (LFM). The multilayered metals and oxides of the back-end-of-line (BEOL), normally used for electronic routing, comprise the structural part of the MEMS. The most important fabrication challenges, modeling approaches and design solutions are discussed. Equations that predict the Q factor, sensitivity, Brownian noise and resonant frequency as a function of temperature, gas pressure and design parameters are presented and validated in characterization tests. A number of the fabricated magnetometers were packaged into Quad Flat No-leads (QFN) packages. We show this process can achieve yields above 95 % when the proper design techniques are adopted. Despite CMOS not being a process for MEMS manufacturing, estimated performance (sensitivity and noise level) is similar or superior to current commercial magnetometers and others built with MEMS processes. Additionally, typical offsets present in Lorentz-force magnetometers were prevented with a shielding electrode, whose efficiency is quantified. Finally, several reliability test results are presented, which demonstrate the robustness against high temperatures, magnetic fields and acceleration shocks.

Neuromorphic computing achieves highly energy-efficient computations while adapting to environmental changes. Processing time series data by spiking neural networks can further reduce the power consumption of neuromorphic computing devices because most of the energy in the network is consumed only when the neuron generates and transmits a spike. In this study, we designed fully analog two-variable spiking neuron and spiking neural network circuits, taking advantage of the physical properties of transistors as analog devices. The energy consumption of the circuit for generating a spike was 22.7 fJ/spike when the MOS transistors were operating in the subthreshold region. The proposed circuits were implemented on an analog very large-scale integrated (VLSI) circuit chip in a 0.18 µm CMOS process. The circuits exhibit complex spike dynamics even under subthreshold operation according to chip measurements. We demonstrated that the spike sequence generated by the spiking neural network circuit was successfully applied to spoken digit recognition tasks via a reservoir computing framework with 14.4 fJ/SOP efficiency. These results provide important insights into edge AI applications of SNN-based neuromorphic hardware.

A first reported complementary metal‐oxide semiconductor (CMOS)‐integrated acceleration sensor obtained through isotropic inter‐metal dielectric (IMD) etching of a back‐end‐of‐line (BEOL) integrated circuit interconnection stack, without any additional substrate etching steps, is presented. The mechanical device composed of a CMOS‐process 8 μm‐thick metal‐via‐metal stack of 135 μm diameter and suspended 2.5 μm over a bottom fixed electrode, has a resonance frequency of 20 kHz, a sensing capacitance of 50 fF with sensitivity 14 aF/G and it is integrated on the same substrate with a simple low‐noise amplifier reaching 25 mG of RMS noise measured from 0.25 to 100 Hz bandwidth.