Waveform generation as part of on-chip built-in self-test (BIST) circuitry often necessitates sufficient linearity without expensive hardware overhead. Achieving high linearity is critical for accurate signal generation, especially in applications requiring high precision, such as biomedical and instrumentation applications. Currently, achieving the high linearity and precision required in signal generators often relies on costly hardware such as automated test equipment (ATE). This paper presents a DAC-based arbitrary waveform generator (AWG). We use a low-cost DAC and a fully digital on-chip testing and calibration approach to nullify the effect of the DAC’s non-linearity on the generated waveform. The ultra-low cost and high linearity benefit of the proposed waveform generator makes it highly suitable for integration into resource-constrained systems. The proposed approach is validated using simulation results of the small-area DAC designed in TSMC 0.18 μm technology and the testing and calibration algorithms implemented in MATLAB. The DAC, designed with a matching accuracy at only the 5-bit level, is able to generate a signal with an ENOB of 12 bits alongside an SFDR and THD surpassing 100 dB. This high level of signal purity is consistently maintained across 100 Monte Carlo simulations, demonstrating the robustness of the architecture against PVT variations as well as random mismatches.

This brief introduces a three-segment resistor string ladder DAC featuring built-in redundancy and sub-radix transfer characteristics. The architecture implements digital calibration to optimize the linearity-resolution tradeoff, achieving substantial area reduction compared to conventional string DAC designs. Measurement and simulation results are presented validating the architecture’s performance. Mathematical analysis is presented revealing a fundamental 1 LSB lower bound on the best achievable post-calibration differential nonlinearity (DNL) for 1-bit redundancy cases. To address this limitation, we present two alternative architectures that demonstrate improved post-calibration DNL performance.

Waveform generation as part of an on-chip built-in self-test (BIST) circuitry often necessitates sufficient linearity without expensive hardware overhead. Achieving high linearity is critical for accurate signal generation, especially in applications requiring high precision, such as biomedical and instrumentation. Currently, achieving the high linearity and precision required in signal generators often relies on costly hardware such as automated test equipment (ATE). This paper presents a DAC based hardware synthesizable arbitrary waveform generator. We use a low-cost DAC and a fully digital on-chip testing and calibration approach to nullify the effect of the DAC’s non-linearity on the generated waveform. The ultra-low cost and high linearity benefit of the proposed waveform generator makes it highly suitable for integration into resource-constrained systems. The proposed approach is validated using simulation results of the small-area DAC designed in TSMC 0.18um technology and the testing and calibration algorithms implemented in MATLAB. The DAC, designed with a matching accuracy at only the 5-bit level, is able to generate a signal with an ENOB of 12 bits alongside a SFDR and THD surpassing 100 dB. This high level of signal purity is consistently maintained across 100 Monte-Carlo simulations, demonstrating the robustness of the architecture against PVT variations as well as random mismatches.

This paper presents a novel methodology for the design and calibration of ultra-compact digital-to-analog converters (DACs), integrating architectural redundancy and a digital calibration algorithm. The proposed calibration approach generates pre-distortion codes that correct both positive and negative nonlinearity errors, even in designs with severe mismatch or relaxed layout constraints. This enables the use of aggressively scaled devices while maintaining high linearity and spectral fidelity. The algorithm is architecture-agnostic and compatible with resistor-string, current-steering, and hybrid DAC structures. It operates with minimal memory, low latency, and supports both foreground and background calibration modes. The method is validated through simulation and silicon measurement of three 14-bit DAC architectures fabricated in TSMC 180 nm CMOS. Post-calibration results demonstrate linearity within ±0.5–1.2 LSB, ENOB up to 13.8 bits, and significant improvements in SNR, SFDR, and THD. The compact layouts—occupying as little as 0.0169 mm²—highlight the scalability of the proposed method for applications such as analog AI accelerators and high-density mixed-signal SoCs.