This paper introduces a systematic approach to the design of Direct Current-to-Digital Converter (DIDC) specifically engineered to overcome the limitations of traditional current measurement methodologies in System-on-Chip (SoC) designs. The proposed DIDC addresses critical challenges such as high power consumption, large area requirements, and the need for intermediate analog signals. By incorporating a current mirror in a cascode topology and managing the current across multiple binary-sized branches with the Successive Approximation Register (SAR) logic, the design achieves precise current measurement. A simple comparator, coupled with an isolation circuit, ensures accurate and reliable sensing. Fabricated using the TSMC 180 nm process, the DIDC achieves 8-bit precision without the need for nonlinearity calibration, showcasing remarkable energy efficiency with an energy per conversion of 1.52 pJ, power consumption of 117 µW, and a compact area of 0.016 mm². This innovative approach not only reduces power consumption and area, but also provides a scalable and efficient solution for next-generation semiconductor technologies. The ability to conduct online measurements during both standard operations and in-field conditions significantly enhances the performance and reliability of SoCs, making this DIDC a promising advancement in the field.

Waveform generation as part of on-chip built-in self-test (BIST) circuitry often necessitates sufficient linearity without expensive hardware overhead. Achieving high linearity is critical for accurate signal generation, especially in applications requiring high precision, such as biomedical and instrumentation applications. Currently, achieving the high linearity and precision required in signal generators often relies on costly hardware such as automated test equipment (ATE). This paper presents a DAC-based arbitrary waveform generator (AWG). We use a low-cost DAC and a fully digital on-chip testing and calibration approach to nullify the effect of the DAC’s non-linearity on the generated waveform. The ultra-low cost and high linearity benefit of the proposed waveform generator makes it highly suitable for integration into resource-constrained systems. The proposed approach is validated using simulation results of the small-area DAC designed in TSMC 0.18 μm technology and the testing and calibration algorithms implemented in MATLAB. The DAC, designed with a matching accuracy at only the 5-bit level, is able to generate a signal with an ENOB of 12 bits alongside an SFDR and THD surpassing 100 dB. This high level of signal purity is consistently maintained across 100 Monte Carlo simulations, demonstrating the robustness of the architecture against PVT variations as well as random mismatches.

This paper introduces a systematic approach to the design of Direct Current-to-Digital Converter (DCDC) specifically engineered to overcome the limitations of traditional current measurement methodologies in System-on-Chip (SoC) designs. The proposed DCDC addresses critical challenges such as high power consumption, large area requirements, and the need for intermediate analog signals. By incorporating a current mirror in a cascode topology and managing the current across multiple binary-sized branches with the Successive Approximation Register (SAR) logic, the design achieves precise current measurement. A simple comparator, coupled with an isolation circuit, ensures accurate and reliable sensing. Fabricated using the TSMC 180 nm process, the DCDC achieves 8-bit precision without the need for nonlinearity calibration, showcasing remarkable energy efficiency with an energy per conversion of 1.52 pJ, power consumption of 117 µW, and a compact area of 0.016 mm². This innovative approach not only reduces power consumption and area, but also provides a scalable and efficient solution for next-generation semiconductor technologies. The ability to conduct online measurements during both standard operations and in-field conditions significantly enhances the performance and reliability of SoCs, making this DCDC a promising advancement in the field.

The first divider in an integer- or fractional-N frequency synthesizer runs at the full oscillator frequency and so constrains both the speed and the power of the loop. Current-mode logic (CML) reaches high speed but draws a constant bias current independent of activity, whereas a fully static-CMOS (all-digital) divider draws only dynamic and leakage current at the cost of much greater timing sensitivity to process, voltage, and temperature (PVT) variation. This paper presents a wide-range all-digital multi-modulus divider in a 22 nm fully depleted silicon-on-insulator (FDSOI) technology, characterized entirely by post-layout and Monte Carlo simulation, together with the methodology that makes the timing-sensitive digital approach robust. The all-digital chain exhibits three PVT failure modes, setup at the slow-hot corner, hold at the fast-cold corner, and internal duty-cycle collapse at the skewed corners; each is predicted analytically and closed by a three-method scheme built on the FDSOI back gate, a per-stage delay trim, and a systematic integral-nonlinearity trim. The divider covers N=8 to 127 at up to 39.5 GHz at the typical corner, with every process corner held at or above 35 GHz by back-gate compensation, the highest speed among the compared dividers and the only one with explicit PVT compensation. At the 33 GHz target it consumes 5.3 mW at N=127 (6.2 GHz/mW) with an activity-scaling supply current, benchmarked against the measured power of published CML dividers. Per-die body-bias and trim raise the Monte Carlo yield from 78% to 99.3%, at 150 fs additive jitter, in a compact 0.005 mm² core.

This paper presents a precision, wide-dynamic-range leakage current sensor tailored for in-situ monitoring of aging mechanisms such as Time-Dependent Dielectric Breakdown (TDDB) in both active and passive components. The proposed architecture supports high-voltage stress and is fully monolithic, integrating a current-to-voltage front-end, tunable gain amplifier, and a successive approximation register (SAR) analog-to-digital converter (ADC). To validate the concept, a discrete-component prototype was implemented and evaluated across a leakage current range of 1nA to 1 μA. The sensor achieves 12-bit resolution with measured integral nonlinearity (INL) and differential nonlinearity (DNL) within ±1.5 LSB and ±0.3 LSB, respectively. Compared to prior monitors, the design enables linear current digitization and compatibility with high-voltage stress, features essential for accurate and scalable TDDB characterization. Applications include embedded reliability monitoring in power converters, analog building blocks, and large-scale aging test arrays.