The capability of multiple valued logic (MVL) circuits to achieve higher storage density when compared to that of existing binary circuits is highly impressive. Recently, MVL circuits have attracted significant attention for the design of digital systems. Carbon nanotube field effect transistors (CNTFETs) have shown great promise for design of MVL based circuits, due to the fact that the scalable threshold voltage of CNTFETs can be utilized easily for the multiple voltage designs. In addition, resistive random access memory (RRAM) is also a feasible option for the design of MVL circuits, owing to its multilevel cell capability that enables the storage of multiple resistance states within a single cell. In this manuscript, a design approach for ternary combinational logic circuits while using CNTFETs and RRAM is presented. The designs of ternary half adder, ternary half subtractor, ternary full adder, and ternary full subtractor are evaluated while using Synopsis HSPICE simulation software with standard 32 nm CNTFET technology under different operating conditions, including different supply voltages, output load variation, and different operating temperatures. Finally, the proposed designs are compared with the state-of-the-art ternary designs. Based on the obtained simulation results, the proposed designs show a significant reduction in the transistor count, decreased cell area, and lower power consumption. In addition, due to the participation of RRAM, the proposed designs have advantages in terms of non-volatility.

Due to the difficulties associated with scaling of silicon transistors, various technologies beyond binary logic processing are actively being investigated. Ternary logic circuit implementation with carbon nanotube field effect transistors (CNTFETs) and resistive random access memory (RRAM) integration is considered as a possible technology option. CNTFETs are currently being preferred for implementing ternary circuits due to their desirable multiple threshold voltage and geometry-dependent properties, whereas the RRAM is used due to its multilevel cell capability which enables storage of multiple resistance states within a single cell. This article presents the 2-trit arithmetic logic unit (ALU) design using CNTFETs and RRAM as the design elements. The proposed ALU incorporates a transmission gate block, a function select block, and various ternary function processing modules. The ALU design optimization is achieved by introducing a controlled ternary adder–subtractor module instead of separate adder and subtractor circuits. The simulations are analyzed and validated using Synopsis HSPICE simulation software with standard 32 nm CNTFET technology under different operating conditions (supply voltages) to test the robustness of the designs. The simulation results indicate that the proposed CNTFET-RRAM integration enables the compact circuit realization with good robustness. Moreover, due to the addition of RRAM as circuit element, the proposed ALU has the advantage of non-volatility.

In this work, a composite strain sensor is fabricated by synthesizing MXene and deposition of polypyrrole on top of the flexible electrospun PVDF nanofibers. The fabricated sensor exhibits a conductive network constructed with MXene and polypyrrole of microcracks network structure, demonstrating its strain sensing properties. The presence of these microcracks serves as mechanical weak points, which leads to sensitivity enhancement, while the electrospun fiber substrate act as a cushion for strain loading under large deformations. The as-prepared MXene@Polypyrrole PVDF sensor has a gauge factor range of 78–355 with a sensing range between 0–100%. Besides strain deformations, the sensor can operate in torsional deformation and human motion, indicating the sensor’s potential as a wearable health monitoring device.

Lately, wearable applications featuring photonic on-chip sensors are on the rise. Among many ways of controlling and/or modulating, the acousto-optic technique is seen to be a popular technique. This paper undertakes the study of different multilayer structures that can be fabricated for realizing an acousto-optic device, the objective being to obtain a high acousto-optic figure of merit (AOFM). By varying the thicknesses of the layers of these materials, several properties are discussed. The study shows that the multilayer thin film structure-based devices can give a high value of electromechanical coupling coefficient (k²) and a high AOFM as compared to the bulk piezoelectric/optical materials. The study is conducted to find the optimal normalised thickness of the multilayer structures with a material possessing the best optical and piezoelectric properties for fabricating acousto-optic devices. Based on simulations and studies of SAW propagation characteristics such as the electromechanical coupling coefficient (k²) and phase velocity (v), the acousto-optic figure of merit is calculated. The maximum value of the acousto-optic figure of merit achieved is higher than the AOFM of all the individual materials used in these layer structures. The suggested SAW device has potential application in wearable and small footprint acousto-optic devices and gives better results than those made with bulk piezoelectric materials.