Since the 1940s, infrared (IR) detection and imaging at wavelengths in the two atmospheric windows of 3 to 5 and 8 to 14 μm has been extensively researched. Through several generations, these detectors have undergone considerable developments and have found use in various applications in different fields including military, space science, medicine and engineering. For the most recently proposed generation, these detectors are required to achieve high-speed detection with spectral and polarization selectivity while operating at room temperature. Antenna coupled IR detectors appear to be the most promising candidate to achieve these requirements and has received substantial attention from research in recent years. This paper sets out to present a review of the antenna coupled IR detector family, to explore the main concepts behind the detectors as well as outline their critical and challenging design considerations. In this context, the design of both elements, the antenna and the sensor, will be presented individually followed by the challenging techniques in the impedance matching between both elements. Some hands-on fabrication techniques will then be explored. Finally, a discussion on the coupled IR detector is presented with the aim of providing some useful insights into promising future work.

A novel × 6 frequency multiplier chain with center frequency of 260 GHz is developed in 40 nm CMOS and measured through this work. The multiplication is accomplished through an x3 frequency multiplier followed by a doubler successive stage. A 4-way signal combiner is employed to enhance the output power, whereas phase shifters are dedicated for compensating the possible phase deviations between the different combined ways, and consequently maintain the combining efficiency. For further output power boosting, the output matching network of 260 GHz frequency doubler is optimized, and a stacked amplifier with 11.5 dBm is employed as a driving amplifier. The multiplier has been fabricated and a peak output power of 3.0 dBm is measured at 260 GHz with a 3-dB bandwidth of 17 GHz.

The fabrication process of a microparabolic reflector using isotropic xenon difluoride etching technique is presented and analysed through this work for developing infrared antenna‐coupled detectors. Although many parametric studies described the behaviour of this process in the literature, the non‐linearity of the process and its dramatic dependency on the pattern definition result in great difficulties when adopting the process for developing a particular structure. The main focus of this work is, therefore, to present a detailed etching analysis as dictated in the proposed design providing the proper etching recipe according to the proposed structure design and its associated masking pattern. Deep insights into the process have been highlighted suggesting the necessity of the process assessment in terms of evaluating the three‐dimensional etched volume rather than the etched depth. This will potentially solve the non‐linearity behaviour and the pattern dependency problem. The optimum etching recipe yields approximately a total volume of 0.354 mm ³ through the proper patterning mask. The resultant parabolic cavities have and in their diameter and depth, respectively, as required for the proposed structure. The integration of a microparabolic reflector with such detectors will potentially enhance the specific detectivity of these detectors.

This paper presents the design and measurements of a 215-252GHz 40nm bulk CMOS frequency doubler with a 6.8dBm deliverable peak output power and a conversion gain of 11.8dB. The designed chip is composed of a 28.5dB gain 6-stages 110GHz power amplifier, an optimized push-push doubler biased in class-C configuration, and an output impedance matching network. A numerical method had been applied here for designing each implemented matching network achieving the optimum matching while maintaining the minimum insertion loss as well. The presented design shows the highest output power among the other sub-THz-designed CMOS counterparts. The design occupies an area of 0.795mm² and shows a total DC power dissipation of 262mW and DC-RF efficiency of 1.87.